VIS
Preliminary
VG4616321B/VG4616322B
262,144x32x2-Bit
CMOS Synchronous Graphic RAM
Figure 26.3 Precharge Termination of a Burst
(Burst Length = 4, 8 or Full page, CAS Latency = 3)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
CLK
CKE
t
CK3
High
CS
RAS
CAS
WE
DSF
BS
A9
RAx
RAy
RAz
A0 ~ A8
RAx
CAx
RAy
CAy
tWR
tRP
DQM
DQ
DAx0 DAx1
Activate
Command
Bank A
Write
Precharge
Command Command
Bank A Bank A
Activate
Command
Bank A
Write Data
is masked
Precharge Termination
of a Write Burst
Read
Command
Bank A
RAz
t
RP
Ay0 Ay1 Ay2
Precharge
Command
Activate
Command
Bank A
Precharge Termination
of a Write Burst
Bank A
Document:1G5-0145
Rev.1
Page 80