WM8772 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8772' PDF : 73 Pages View PDF
WM8772EFT – 32 LEAD TQFP
Production Data
ADCBCLK/
DACBCLK
(Outputs)
ADCLRC/
DACLRC
(Outputs)
DOUT
tDL
tDDA
DIN1/2/3
tDST
tDHT
Figure 39 Digital Audio Data Timing – Master Mode
Test Conditions
AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, DGND = 0V, TA = +25oC, Master Mode, fs = 48kHz, DACMCLK and
ADCMCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
ADCLRC/DACLRC
tDL
propagation delay from
ADCBCLK/DACBCLK
falling edge
DOUT propagation delay
tDDA
from ADCBCLK falling edge
DIN1/2/3 setup time to
tDST
DACBCLK rising edge
DIN1/2/3 hold time from
tDHT
DACBCLK rising edge
TEST CONDITIONS
Table 14 Digital Audio Data Timing – Master Mode
MIN
TYP
MAX
UNIT
0
10
ns
0
10
ns
10
ns
10
ns
w
PD Rev 4.2 October 2005
44
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