WM8772 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8772' PDF : 73 Pages View PDF
WM8772EFT – 32 LEAD TQFP
Production Data
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND = 0V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, DACMCLK and ADCMCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
Audio Data Input Timing Information
ADCBCLK/DACBCLK cycle
tBCY
time
ADCBCLK/DACBCLK pulse
tBCH
width high
ADCBCLK/DACBCLK pulse
tBCL
width low
ADCLRC/DACLRC set-up
time to
ADCBCLK/DACBCLK rising
edge
tLRSU
ADCLRC/DACLRC hold
tLRH
time from
ADCBCLK/DACBCLK rising
edge
DIN1/2/3 set-up time to
tDS
DACBCLK rising edge
DIN1/2/3 hold time from
tDH
DACBCLK rising edge
DOUT propagation delay
tDD
from ADCBCLK falling edge
TEST CONDITIONS
Table 15 Digital Audio Data Timing – Slave Mode
MIN
TYP
MAX
UNIT
50
ns
20
ns
20
ns
10
ns
10
ns
10
ns
10
ns
0
10
ns
MPU INTERFACE TIMING
ML/I2S
MC/IWL
tSCY
tSCH
tSCL
tCSL
tCSH
tCSS
tSCS
MD/DM
tDSU
tDHO
Figure 42 SPI Compatible Control Interface Input Timing
LSB
w
PD Rev 4.2 October 2005
46
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