WM8772 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8772' PDF : 73 Pages View PDF
WM8772EFT – 32 LEAD TQFP
Production Data
I2S MODE
In I2S mode, the MSB of DIN1/2/3 is sampled by the WM8772EFT on the second rising edge of
BCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and changes on
the first falling edge of BCLK following an ADCLRC transition and may be sampled on the rising edge
of BCLK. ADCLRC and DACLRC are low during the left samples and high during the right samples.
1/fs
DACLRC/
ADCLRC
LEFT CHANNEL
DACBCLK/
ADCBCLK
DIN1/2/3/
DOUT
1 BCLK
123
MSB
n-2 n-1 n
LSB
Figure 49 I2S Mode Timing Diagram
RIGHT CHANNEL
1 BCLK
123
MSB
n-2 n-1 n
LSB
DSP MODE A
In DSP mode A, the MSB of DAC channel 1 left data is sampled by the WM8772EFT on the second
rising edge on DACBCLK following a DACLRC rising edge. DAC channel 1 right and DAC channels 2
and 3 data follow DAC channel 1 left data (Figure 50).
Figure 50 DSP Mode Audio Interface - Mode A Slave, DAC
1 BCLK
1/fs
DACLRC
DACBCLK
DIN1
CHANNEL 1
LEFT
CHANNEL 1
RIGHT
CHANNEL 2
LEFT
12
MSB
n-1 n 1 2
LSB
n-1 n 1 2
Input Word Length (IWL)
1 BCLK
CHANNEL 3
RIGHT
NO VALID DATA
n-1 n
Figure 51 DSP Mode Audio Interface - Mode A Master, DAC
w
PD Rev 4.2 October 2005
54
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