WM8772 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8772' PDF : 73 Pages View PDF
Production Data
WM8772EFT – 32 LEAD TQFP
CONTROL INTERFACE REGISTERS
ATTENUATOR CONTROL MODE
Setting the ATC register bit causes the left channel attenuation settings to be applied to both left and
right channel DACs from the next audio input sample. No update to the attenuation registers is
required for ATC to take effect.
REGISTER ADDRESS BIT
0000010
3
DAC Channel Control
LABEL
ATC
DEFAULT
0
DESCRIPTION
Attenuator Control Mode:
0: Right channels use right
attenuations
1: Right channels use left
attenuations
INFINITE ZERO DETECT ENABLE
Setting the IZD register bit will enable the internal infinite zero detect function:
REGISTER ADDRESS BIT LABEL DEFAULT
DESCRIPTION
0000010
4
IZD
DAC Channel Control
0
Infinite zero mute enable
0: Disable infinite zero mute
1: Enable infinite zero mute
With IZD enabled, applying 1024 consecutive zero input samples to each input will cause the
relevant DAC to be muted to VMID. Mute will be removed as soon as that channel receives a non-zero
input.
DAC OUTPUT CONTROL
The DAC output control word determines how the left and right inputs to the audio Interface are
applied to the left and right DACs:
REGISTER ADDRESS BIT
0000010
8:5
DAC Control
LABEL
PL[3:0]
DEFAULT
1001
PL[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
DESCRIPTION
Left
Output
Right
Output
Mute
Mute
Left
Mute
Right
Mute
(L+R)/2 Mute
Mute
Left
Left
Left
Right
Left
(L+R)/2 Left
Mute
Right
Left
Right
Right
Right
(L+R)/2 Right
Mute
(L+R)/2
Left
(L+R)/2
Right
(L+R)/2
(L+R)/2 (L+R)/2
w
PD Rev 4.2 October 2005
59
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