WM8804GEDS/V View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8804GEDS/V' PDF : 66 Pages View PDF
Production Data
OSC
CLK
(MHz)
PRE-
SCALE
F1
(MHz)
F2
(MHz)
WM8804
R
PLL_N PLL_K FREQ MCLK MCLK CLKOUT
CLK
(Hex)
(Hex)
MODE
DIV
(MHz)
DIV
OUT
[1:0]
[1:0]
(MHz)
12
0
12
98.304 8.192
8
12
0
12
98.304 8.192
8
12
0
12
98.304 8.192
8
12
0
12
98.304 8.192
8
12
0
12
98.304 8.192
8
24
1
12
90.3168 7.5264
7
24
1
12
90.3168 7.5264
7
24
1
12
90.3168 7.5264
7
24
1
12
90.3168 7.5264
7
24
1
12
90.3168 7.5264
7
27
1
13.5 98.304 7.2818
7
27
1
13.5 98.304 7.2818
7
27
1
13.5 90.3168 6.6901
6
27
1
13.5 90.3168 6.6901
6
Table 23 User Mode PLL Configuration Examples
C49BA
00
C49BA
10
C49BA
10
C49BA
10
C49BA
10
21B089
01
21B089
10
21B089
10
21B089
10
21B089
10
1208A5
10
1208A5
10
2C2B24
10
2C2B24
10
1
24.576
01
49.152
0
12.288
00
24.576
1
6.144
01
12.288
0
12.288
10
6.144
1
6.144
11
3.072
0
22.5792
00
45.1584
0
11.2896
00
22.5792
1
5.6448
01
11.2896
0
11.2896
10
5.6448
1
5.6448
11
2.8224
0
12.288
01
12.288
1
6.144
10
6.144
0
11.2896
01
11.2896
1
5.6448
10
5.6448
When considering settings not shown in this table, the key configuration parameters which must be
selected for optimum operation are:
• 90MHz ≤ f2 ≤ 100MHz
• 5 ≤ PLL_N ≤ 13
• OSCCLOCK = 10 to 14.4MHz or 16.28 to 27MHz
PLL INTEGER AND FRACTIONAL CONTROL MODES
The PLL can be operated in either fractional or integer control modes. In PLL User Mode, it is
recommended that the PLL should be operated in fractional control mode at all times. When
the S/PDIF receiver is enabled, the PLL must be operated in fractional control mode.
REGISTER BIT
ADDRESS
R7
2
PLL5
07h
LABEL
FRACEN
DEFAULT
1
Table 24 PLL Fractional/Integer Mode Select
DESCRIPTION
Integer/Fractional PLL Mode
Select
0 = Integer PLL (PLL_N value used,
PLL_K value ignored)
1 = Fractional PLL (both PLL_N and
PLL_K values used)
Note: FRACEN must be set to
enable the fractional PLL when
using S/PDIF Receive Mode.
MASTER CLOCK (MCLK)
The master clock (MCLK) signal is used to supply reference clock signals to the following circuit
blocks:
• The Digital Audio Interface
• The S/PDIF Transmitter
The master clock (MCLK) pin can be configured as either a clock input or output depending on the
digital audio interface mode as shown in Table 25.
w
PD, Rev 4.5, March 2009
25
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