WM8804GEDS/V View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8804GEDS/V' PDF : 66 Pages View PDF
WM8804
REGISTER BIT
ADDRESS
R28
6
AIFRX
1Ch
LABEL
AIF_MS
Table 25 Audio Interface Mode Select
DEFAULT
Production Data
DESCRIPTION
0
Audio Interface Mode Select
0 = Slave mode – MCLK Input
1 = Master mode – MCLK Output
When MCLK is configured as an output, the MCLK source and rate can be selected using the control
bits shown in Table 26. The MCLK rate select can only be used when the MCLK output source is
selected as the PLL clock. If the oscillator clock is selected as the PLL source, the MCLK frequency
is equal to the oscillator clock frequency.
REGISTER BIT
ADDRESS
R7
3
PLL5
07h
LABEL
MCLKDIV
R8
7
MCLKSRC
PLL6
08h
Table 26 Master Clock Output Control
DEFAULT
DESCRIPTION
0
MCLK Divider Select
(Only valid when CLK2 is selected
as MCLK output source)
See Table 27 for MCLKDIV
configuration in PLL user mode.
See Table 28 for MCLKDIV
configuration in PLL S/PDIF receive
mode.
0
MCLK Output Source select
0 = Select CLK2
1 = Select OSCCLK
FREQMODE[1:0]
00
01
10
11
F2 TO CLK1 DIVISION FACTOR
CLKOUTDIV[1:0]
00
01
10
11
÷2
÷2
÷4
÷8
÷2
÷4
÷8
÷16
÷4
÷8
÷16
÷32
÷6
÷12
÷24
÷48
Table 27 PLL User Mode Clock Divider Configuration
F2 TO CLK2 DIVISION FACTOR
MCLKDIV
0
1
÷2
÷4
÷4
÷8
÷8
÷16
÷12
÷24
CLKOUTDIV[1:0]
00
01
10
11
CLK1 FREQUENCY
512fs
256fs
128fs
64fs
MCLKDIV
0
1
Table 28 PLL S/PDIF Receive Mode Clock Divider Configuration
CLK2 FREQUENCY
256fs
128fs
Note: The fs values shown above are relative to the S/PDIF recovered sample rate.
When MCLK is configured as an input, the reference clock rate for the S/PDIF transmitter (when the
digital audio interface received data is configured as the S/PDIF transmitter data source) is controlled
by the frequency of the MCLK signal at the MCLK pin.
Refer to the “Digital Audio Interface” datasheet section for details of configuring MCLK for appropriate
digital audio interface operation.
CLOCK OUTPUT (CLKOUT)
The high-drive clock output (CLKOUT) pin can be used as a clock output. This pin is intended to be
used as a clock source pin for providing the central clock reference for an audio system.
The CLKOUT clock source can be selected from either the OSCCLK or CLK1 signals. The control
bits for the CLKOUT signal are shown in Table 29.
w
PD, Rev 4.5, March 2009
26
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