WM8804GEDS/V View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8804GEDS/V' PDF : 66 Pages View PDF
Production Data
WM8804
Master/slave mode is selected with the following register:
REGISTER BIT LABEL DEFAULT
ADDRESS
R28
6 AIF_MS
0
AIFRX
1Ch
7 SYNC_
0
OFF
Table 55 Master/Slave Mode Select Register
DESCRIPTION
Audio Interface Master/Slave Mode Select
0 = Slave mode – MCLK, LRCLK and BCLK
are inputs
1 = Master mode – MCLK, LRCLK and BCLK
are outputs
Audio Interface Clock Output Enable
Enables BCLK and LRCLK out when external
S/PDIF source has been removed (master
mode only)
0 = LRCLK, BCLK are not output when S/PDIF
source has been removed
1= LRCLK, BCLK output when S/PDIF source
has been removed
When operating in master mode, then the BCLK and LRCLK are derived from the sample rate of the
S/PDIF received signal. If the S/PDIF receive data signal is removed (unplugged) then by default the
AIF BCLK and LRCLK will not be output. This can be reconfigured to allow these clocks to continue
outputting when the source is removed using the SYNC_OFF bit in register R28.
AUDIO DATA FORMATS
Five interface formats are supported:
• Left Justified Mode
• Right Justified Mode
• I2S Mode
• DSP Mode A
• DSP Mode B
The MSB is sent first in all formats. Word lengths of 16, 20 and 24 bits are supported.
Audio data for each stereo channel is clocked with the BCLK signal. Data is time multiplexed with the
LRCLK, indicating whether the left or right channel data is present. The LRCLK is also used as a
timing reference to indicate the beginning or end of the data words.
In Left Justified, Right Justified and I2S modes the minimum number of BCLKs per LRCLK period is
two times the number of bits in the selected word length. LRCLK must be high for a minimum of n
BCLKs and low for a minimum of n BCLKs, where n is the number of bits in an audio word. Any mark
to space ratio on LRCLK is acceptable provided the above requirements are met.
The data may also be output in DSP Mode A or Mode B, with LRCLK used as a frame sync to
identify the MSB of the first word. The minimum number of BCLKs per LRCLK period is two times the
number of bits in the word length.
LEFT JUSTIFIED MODE
In Left Justified mode, the MSB of DIN is sampled by the WM8804 on the first rising edge of BCLK
following an LRCLK transition. The MSB of the output data (DOUT) changes on the same falling
edge of BCLK as LRCLK and may be sampled on the next rising edge of BCLK. LRCLK is high
during the left samples and low during the right samples (Figure 18).
w
PD, Rev 4.5, March 2009
45
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