WM8804GEDS/V View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8804GEDS/V' PDF : 66 Pages View PDF
Production Data
WM8804
DSP MODE A
In DSP Mode A, the MSB of the left channel data is sampled by the WM8804 on the second rising
edge of BCLK following an LRCLK rising edge. The right channel data follows the left channel data
(Figure 21).
The MSB of the left channel of the output data changes on the first falling edge of BCLK following a
low to high LRCLK transition and may be sampled on the rising edge of BCLK. The right channel
data is contiguous with the left channel data (Figure 21).
1 BCLK
1/fs
1 BCLK
LRCLK
BCLK
DIN / DOUT
LEFT
RIGHT
12
MSB
n-1 n 1 2
LSB
Input Word Length (IWL)
n-1 n
NO VALID DATA
Figure 21 DSP Mode A
DSP MODE B
In DSP Mode B, the MSB of the left channel data is sampled by the WM8804 on the first BCLK rising
edge following a LRCLK rising edge. The right channel data follows the left channel data (Figure 22).
The MSB of the output data changes on the same falling edge of BCLK as the low to high LRCLK
transition and may be sampled on the rising edge of BCLK. The right channel data is contiguous with
the left channel data (Figure 22).
1/fs
LRCLK
BCLK
DIN / DOUT
LEFT
RIGHT
12
MSB
n-1 n 1 2
LSB
Input Word Length (IWL)
n-1 n
NO VALID DATA
1
Figure 22 DSP Mode B
w
PD, Rev 4.5, March 2009
47
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