WM8804GEDS/V View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8804GEDS/V' PDF : 66 Pages View PDF
WM8804
LRCLK
BCLK
LEFT CHANNEL
Production Data
1/fs
RIGHT CHANNEL
DIN / DOUT
123
MSB
n-2 n-1 n
LSB
123
MSB
n-2 n-1 n
LSB
Figure 18 Left Justified Mode
RIGHT JUSTIFIED MODE
In Right Justified Mode, the LSB of DIN is sampled by the WM8804 on the rising edge of BCLK
preceding an LRCLK transition. The LSB of the output data (DOUT) changes on the falling edge of
BCLK preceding an LRCLK transition, and may be sampled on the next rising edge of BCLK. LRCLK
is high during the left samples and low during the right samples (Figure 19).
1/fs
LRCLK
BCLK
LEFT CHANNEL
RIGHT CHANNEL
DIN / DOUT
123
MSB
n-2 n-1 n
LSB
123
MSB
n-2 n-1 n
LSB
Figure 19 Right Justified Mode
I2S MODE
In I2S Mode, the MSB of DIN is sampled by the WM8804 on the second rising edge of BCLK
following an LRCLK transition. The MSB of the output data changes on the first falling edge of BCLK
following an LRCLK transition, and may be sampled on the next rising edge of BCLK. LRCLK is low
during the left samples and high during the right samples (Figure 20).
LRCLK
BCLK
DIN / DOUT
LEFT CHANNEL
1/fs
RIGHT CHANNEL
1 BCLK
123
MSB
n-2 n-1 n
LSB
1 BCLK
123
MSB
n-2 n-1 n
LSB
Figure 20 I2S Mode
w
PD, Rev 4.5, March 2009
46
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