WM8956 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8956' PDF : 80 Pages View PDF
WM8956
Production Data
CLASS D SPEAKER OUTPUTS
The class D speaker outputs SPK_LN/SPK_LP and SPK_RN/SPK_RP can drive 1W into 8 BTL
speakers. Class D outputs reduce power consumption and maximise efficiency by reducing power
dissipated in the output drivers, delivering most of the power directly to the load. This is achieved by
pulse width modulation (PWM) of a high frequency square wave, allowing the audio signal level to be
set by controlling the pulse width. The frequency of the output waveform is controlled by DCLKDIV,
and is derived from SYSCLK.
When the speakers are close to the device (typically less than about 100mm) the internal filtering
effects of the speaker can be used. Where signals are routed over longer distances, it is
recommended to use additional passive filtering, positioned close to the WM8956, to reduce EMI. See
"Applications Information" for more information on EMI reduction.
REGISTER
ADDRESS
R8 (08h)
Clocking (2)
BIT
LABEL
8:6 DCLKDIV
R49 (31h)
Class D
Control (1)
7:6 SPK_OP_EN
[1:0]
Table 22 Class D Control Registers
DEFAULT
DESCRIPTION
111
Controls clock division from
SYSCLK to generate suitable class
D clock.
000 = Reserved
001 = SYSCLK / 2
010 = SYSCLK / 3
011 = SYSCLK / 4
100 = SYSCLK / 6
101 = SYSCLK / 8
110 = SYSCLK / 12
111 = SYSCLK / 16
00
Enable Class D Speaker Outputs
00 = Off
01 = Left speaker only
10 = Right speaker only
11 = Left and right speakers enabled
The class D outputs require a PWM switching clock, which is derived from SYSCLK. This clock
should not be altered or disabled while the class D outputs are enabled.
See "Clocking and Sample Rates" for more information.
w
PD, November 2011, Rev 4.1
36
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