WM8956 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8956' PDF : 80 Pages View PDF
Production Data
REGISTER BIT
ADDRESS
Additional 6
Control (2)
LABEL
HPSWEN
5
HPSWPOL
4
3
TRIS
2:0
R25 (19h) 8:7
Power
Mgmt (1)
VMIDSEL[1:0]
6
VREF
5
AINL
4
AINR
3:2
1
MICB
0
DIGENB
R26 (1Ah) 8
Power
Mgmt (2)
7
DACL
DACR
6
LOUT1
5
ROUT1
4
SPKL
3
SPKR
2
w
WM8956
DEFAULT
DESCRIPTION
REFER TO
0
Headphone Switch Enable
0 = Headphone switch disabled
Headphone Jack
Detect
1 = Headphone switch enabled
0
Headphone Switch Polarity
0 = HPDETECT high = headphone
Headphone Jack
Detect
1 = HPDETECT high = speaker
Reserved
0
Switches DACLRC and BCLK to inputs.
Audio Interface
0 = DACLRC and BCLK are inputs (slave mode) Control
or outputs (master mode)
1 = DACLRC and BCLK are inputs
000
Reserved
00
Vmid Divider Enable and Select
00 = Vmid disabled (for OFF mode)
Power
Management
01 = 2 x 50k divider enabled (for playback /
record)
10 = 2 x 250k divider enabled (for low-power
standby)
11 = 2 x 5k divider enabled (for fast start-up)
0
VREF (necessary for all other functions)
Power
0 = Power down
Management
1 = Power up
0
Analogue in PGA Left
0 = Power down
1 = Power up
Power
Management
0
Analogue in PGA Right
0 = Power down
1 = Power up
Power
Management
00
Reserved
0
MICBIAS
0 = Power down
Power
Management
1 = Power up
0
Master Clock Disable
0 = Master clock enabled
1 = Master clock disabled
Power
Management
0
DAC Left
0 = Power down
1 = Power up
Power
Management
0
DAC Right
0 = Power down
1 = Power up
Power
Management
0
LOUT1 Output Buffer
0 = Power down
Power
Management
1 = Power up
0
ROUT1 Output Buffer
0 = Power down
Power
Management
1 = Power up
0
SPK_LP/SPK_LN Output Buffers
0 = Power down
Power
Management
1 = Power up
0
SPK_RP/SPK_RN Output Buffers
0 = Power down
Power
Management
1 = Power up
0
Reserved
PD, November 2011, Rev 4.1
65
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