WM8956 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8956' PDF : 80 Pages View PDF
WM8956
REGISTER BIT
ADDRESS
1
LABEL
OUT3
0
PLL_EN
R27 (1Bh) 8:7
Additional 6
Control (3)
VROI
5
4
3
OUT3CAP
2:0
R28 (1Ch) 8
Anti-Pop 7
POBCTRL
6:5
4
BUFDCOPEN
3
BUFIOEN
2
SOFT_ST
1
0
HPSTBY
R29 (1Dh) 8:7
6
DISOP
5:4 DRES[1:0]
3:0
R30 (1Eh) 8:0
w
DEFAULT
DESCRIPTION
Production Data
REFER TO
0
0
00
0
0
0
0
000
0
0
00
0
0
0
0
0
00
0
00
0000
000000000
OUT3 Output Buffer
0 = Power down
1 = Power up
PLL Enable
0 = Power down
1 = Power up
Reserved
VREF to Analogue Output Resistance (Disabled
Outputs)
0 = 500 VMID to output
1 = 20k VMID to output
Reserved
Reserved
Capless Mode Headphone Switch Enable
0 = OUT3 unaffected by jack detect events
1 = OUT3 enabled and disabled together with
HP_L and HP_R in response to jack detect
events
Reserved
Reserved
Selects the bias current source for output
amplifiers and VMID buffer
0 = VMID / R bias
1 = VGS / R bias
Reserved
Enables the VGS / R current generator
0 = Disabled
1 = Enabled
Enables the VGS / R current generator and the
analogue input and output bias
0 = Disabled
1 = Enabled
Enables VMID soft start
0 = Disabled
1 = Enabled
Reserved
Headphone Amplifier Standby
0 = Standby mode disabled (Normal operation)
1 = Standby mode enabled
Reserved
Discharges the DC-blocking headphone
capacitors on HP_L and HP_R
0 = Enabled
1 = Disabled
DRES determines the value of the resistors used
to discharge the DC-blocking headphone
capacitors when DISOP=1
D600
D200
Resistance
0
0
400
0
1
200
1
0
600
1
1
150
Reserved
Reserved
Power
Management
Power
Management
Enabling the
Outputs
Headphone Jack
Detect
PD, November 2011, Rev 4.1
66
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