WM8956 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8956' PDF : 80 Pages View PDF
Production Data
WM8956
SYSCLK
(=MCLK OR PLL OUTPUT)
(MHz)
12.288
11.2896
2.048
DACDIV
000 (=1)
001 (=1.5)
010 (=2)
011 (=3)
100 (=4)
101 (=5.5)
110 (=6)
111
000 (=1)
001 (=1.5)
010 (=2)
011 (=3)
100 (=4)
101 (=5.5)
110 (=6)
111
000 (=1)
001 (=1.5)
010 (=2)
011 (=3)
100 (=4)
101 (=5.5)
110 (=6)
111
Table 32 DAC Sample Rates
DAC SAMPLE RATE
(kHz)
48
32
24
16
12
(Not used)
8
Reserved
44.1
(Not used)
22.05
(Not used)
11.025
8.018
(Not used)
Reserved
8
(Not used)
(Not used)
(Not used)
(Not used)
(Not used)
(Not used)
Reserved
When operating in slave mode, the host device must provide sufficient BCLK cycles to transfer
complete data words to the DACs.
Table 33 shows the maximum word lengths supported for a given SYSCLK and BCLKDIV, assuming
that the DACs are running at maximum rate (i.e. DACDIV[2:0]=000).
w
PD, November 2011, Rev 4.1
51
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