Production Data
WM8956
REGISTER
ADDRESS
R25 (19h)
Power
Management
(1)
R26 (1Ah)
Power
Management
(2)
BIT
LABEL
8:7 VMIDSEL
6
VREF
5
AINL
4
AINR
1
MICB
0
DIGENB
8
DACL
7
DACR
6
LOUT1
5
ROUT1
4
SPKL
3
SPKR
1
OUT3
DEFAULT
DESCRIPTION
00
Vmid Divider Enable and Select
00 = Vmid disabled (for OFF mode)
01 = 2 x 50k divider enabled (for playback /
record)
10 = 2 x 250k divider enabled (for low-
power standby)
11 = 2 x 5k divider enabled (for fast start-
up)
0
VREF (necessary for all other functions)
0 = Power down
1 = Power up
0
Analogue Input PGA and Boost Left
0 = Power down
1 = Power up
(Note: LMIC must also be set to enable the
PGA)
0
Analogue Input PGA and Boost Right
0 = Power down
1 = Power up
(Note: RMIC must also be set to enable the
PGA)
0
MICBIAS
0 = Power down
1 = Power up
0
Master Clock Disable
0 = Master clock enabled
1 = Master clock disabled
0
DAC Left
0 = Power down
1 = Power up
0
DAC Right
0 = Power down
1 = Power up
0
LOUT1 Output Buffer
0 = Power down
1 = Power up
0
ROUT1 Output Buffer
0 = Power down
1 = Power up
0
SPK_LP/SPK_LN Output PGA.
0 = Power down
1 = Power up
(Note: Speaker output also requires
SPK_OP_EN[0] to be set)
0
SPK_RP/SPK_RN Output PGA
0 = Power down
1 = Power up
(Note: Speaker output also requires
SPK_OP_EN[1] to be set)
0
OUT3 Output Buffer
0 = Power down
1 = Power up
w
PD, November 2011, Rev 4.1
57