WM8956 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8956' PDF : 80 Pages View PDF
WM8956
Production Data
SYSCLK
(=MCLK OR PLL OUTPUT)
(MHz)
12.288
11.2896
BCLKDIV[3:0]
0000 (=1)
0001 (=1.5)
0010 (=2)
0011 (=3)
0100 (=4)
0101 (=5.5)
0110 (=6)
0111 (=8)
1000 (=11)
1001 (=12)
1010 (=16)
1011 (=22)
1100 (=24)
1101 (=32)
1110 (=32)
1111 (=32)
0000 (=1)
0001 (=1.5)
0010 (=2)
0011 (=3)
0100 (=4)
0101 (=5.5)
0110 (=6)
0111 (=8)
1000 (=11)
1001 (=12)
1010 (=16)
1011 (=22)
1100 (=24)
1101 (=32)
1110 (=32)
1111 (=32)
BCLK RATE MAXIMUM WORD LENGTH
(MASTER MODE) (AT MAXIMUM DAC
(MHz)
SAMPLE RATE)
12.288
32
8.192
32
6.144
32
4.096
32
3.072
32
2.2341818
20
2.048
20
1.536
16
1.117091
8
1.024
8
0.768
8
0.558545
N/A
0.512
N/A
0.384
N/A
0.384
N/A
0.384
N/A
11.2896
32
7.5264
32
5.6448
32
3.7632
32
2.8224
32
2.052655
20
1.8816
20
1.4112
16
1.026327
8
0.9408
8
0.7056
8
0.513164
N/A
0.4704
N/A
0.3528
N/A
0.3528
N/A
0.3528
N/A
Table 33 BCLK Divider in Master Mode
w
PD, November 2011, Rev 4.1
52
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