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WM8956 View Datasheet(PDF) - Cirrus Logic

Part Name
Description
MFG CO.
'WM8956' PDF : 80 Pages View PDF
WM8956
Production Data
CONTROL INTERFACE
2-WIRE SERIAL CONTROL INTERFACE
The WM8956 is controlled by writing to registers through a 2-wire serial control interface. A control
word consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register
is accessed. The remaining 9 bits (B8 to B0) are data bits, corresponding to the 9 bits in each control
register. Many devices can be controlled by the same bus, and each device has a unique 7-bit
address (this is not the same as the 7-bit address of each register in the WM8956).
The device address is 0011010 (0x34h).
The WM8956 operates as a slave device only. The controller indicates the start of data transfer with a
high to low transition on SDIN while SCLK remains high. This indicates that a device address and
data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight
bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the
address of the WM8956 and the R/W bit is ‘0’, indicating a write, then the WM8956 responds by
pulling SDIN low on the next clock pulse (ACK). If the address is not recognised or the R/W bit is ‘1’,
the WM8956 returns to the idle condition and wait for a new start condition and valid address.
Once the WM8956 has acknowledged a correct address, the controller sends the first byte of control
data (B15 to B8, i.e. the WM8956 register address plus the first bit of register data). The WM8956
then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then
sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the
WM8956 acknowledges again by pulling SDIN low.
The transfer of data is complete when there is a low to high transition on SDIN while SCLK is high.
After receiving a complete address and data sequence the WM8956 returns to the idle state and
waits for another start condition. If a start or stop condition is detected out of sequence at any point
during data transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.
SDIN
SCLK
START
DEVICE ADDRESS RD / WR ACK
(7 BITS)
BIT
(LOW)
CONTROL BYTE 1
(BITS 15 TO 8)
ACK
(LOW)
CONTROL BYTE 2
(BITS 7 TO 0)
ACK
(LOW)
register address and
1st register data bit
remaining 8 bits of
register data
STOP
Figure 35 2-Wire Serial Control Interface
POWER MANAGEMENT
The WM8956 has three control registers that allow users to select which functions are active. For
minimum power consumption, unused functions should be disabled. To avoid any pop or click noise,
it is important to enable or disable functions in the correct order (see Applications Information).
VMIDSEL is the enable for the Vmid reference, which defaults to disabled and can be enabled as a
2x50kpotential divider or, for low power maintenance of Vref when all other blocks are disabled, as
a 2x250kpotential divider.
w
PD, November 2011, Rev 4.1
56
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