WM8956 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8956' PDF : 80 Pages View PDF
WM8956
Production Data
REGISTER BIT
LABEL
ADDRESS
R52 (34h)
4
PLLPRESCALE
PLL N value
3:0 PLLN
R53 (35h)
5:0
PLL K value
(1)
R54 (36h)
8:0
PLL K Value
(2)
R55 (37h)
8:0
PLL K Value
(3)
PLLK [23:16]
PLLK [15:8]
PLLK [7:0]
DEFAULT
DESCRIPTION
0
Divide MCLK by 2 before input to
PLL
0 = Divide by 1
1 = Divide by 2
8h
Integer (N) part of PLL input/output
frequency ratio. Use values greater
than 5 and less than 13.
31h
Fractional (K) part of PLL1
input/output frequency ratio (treat as
one 24-digit binary number).
26h
E9h
Table 36 PLL Frequency Ratio Control
The PLL performs best when f2 is between 90MHz and 100MHz. Its stability peaks at N=8. Some
example settings are shown in Table 37.
MCLK
(MHz)
(f1)
DESIRED OUTPUT
(SYSCLK)
(MHz)
f2
(MHz)
R
N
K
12
12
13
13
14.4
14.4
19.2
19.2
19.68
19.68
19.8
19.8
24
24
26
26
27
27
11.2896
12.288
11.2896
12.288
11.2896
12.288
11.2896
12.288
11.2896
12.288
11.2896
12.288
11.2896
12.288
11.2896
12.288
11.2896
12.288
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
90.3168
98.304
Table 37 PLL Frequency Examples
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
1
2
4
2
2
4
2
2
4
2
2
4
2
2
4
2
2
4
2
2
4
2
2
4
2
2
4
2
2
4
2
2
4
2
2
4
2
2
4
7.5264
8.192
6.947446
7.561846
6.272
6.826667
9.408
10.24
9.178537
9.990243
9.122909
9.929697
7.5264
8.192
6.947446
7.561846
6.690133
7.281778
7h
86C226h
8h
3126E8h
6h
F28BD4h
7h
8FD525h
6h
45A1CAh
6h
D3A06Eh
9h
6872AFh
Ah
3D70A3h
9h
2DB492h
9h
FD809Fh
9h
1F76F7h
9h
EE009Eh
7h
86C226h
8h
3126E8h
6h
F28BD4h
7h
8FD525h
6h
B0AC93h
7h
482296h
w
PD, November 2011, Rev 4.1
54
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