Production Data
Table 38 Example Clocking Schemes
WM8956
Device running in master mode with 24-bit data
MCLK input at 12.288MHz
DAC running at fs=48kHz
BCLK running at 64fs
Device running in slave mode with 24-bit data
MCLK input at 12.288MHz
DAC running at fs=48kHz
BCLK supplied from host at 64fs in this example
Device running in master mode with 24-bit data
MCLK input at 11.2896MHz
DAC running at fs=44.1kHz
BCLK running at 64fs in this example
Device running in slave mode with 24-bit data
MCLK input at 11.2896MHz
DAC running at fs=44.1kHz
BCLK supplied from host at 64fs in this example.
Device running in master mode with 24-bit data
MCLK input at 12MHz
PLL Enabled and configured for SYSCLK=11.2896MHz
DAC running at fs=44.1kHz
BCLK running at 64fs in this example
Class D clocks running at 705.6kHz
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PD, November 2011, Rev 4.1
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