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Part Name
Description
WM8956 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
WM8956
Hi-Fi DAC with 1W Stereo Class D Speaker Drivers and Headphone Drivers
Cirrus Logic
'WM8956' PDF : 80 Pages
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Production Data
REGISTER MAP
WM8956
REGISTER
R0 (00h)
R1 (01h)
R2 (02h)
R3 (03h)
R4 (04h)
R5 (05h)
R6 (06h)
R7 (07h)
R8 (08h)
R9 (09h)
R10 (0Ah)
R11 (0Bh)
R12 (0Ch)
R13 (0Dh)
R14 (0Eh)
R15 (0Fh)
R16 (10h)
R17 (11h)
R18 (12h)
R19 (13h)
R20 (14h)
R21 (15h)
R22 (16h)
R23 (17h)
R24 (18h)
R25 (19h)
R26 (1Ah)
R27 (1Bh)
R28 (1Ch)
R29 (1Dh)
R30 (1Eh)
R31 (1Fh)
R32 (20h)
R33 (21h)
R34 (22h)
R35 (23h)
R36 (24h)
R37 (25h)
R38 (26h)
R39 (27h)
R40 (28h)
R41 (29h)
R42 (2Ah)
R43 (2Bh)
R44 (2Ch)
R45 (2Dh)
R46 (2Eh)
R47 (2Fh)
R48 (30h)
R49 (31h)
R50 (32h)
R51 (33h)
R52 (34h)
R53 (35h)
R54 (36h)
R55 (37h)
remarks
Left Input volume
Right Input volume
LOUT1 volume
ROUT1 volume
Clocking (1)
DAC Control (CTR1)
DAC Control (CTR2)
Audio Interface
Clocking (2)
Audio Interface
Left DAC volume
Right DAC volume
Reserved
Reserved
Reserved
Reset
3D control
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Additional control(1)
Additional control(2)
Pwr Mgmt (1)
Pwr Mgmt (2)
Additional Control (3)
Anti-pop 1
Anti-pop 2
Reserved
Reserved
L input signal path
R input signal path
Left out Mix (1)
Reserved
Reserved
Right out Mix (2)
Mono out Mix (1)
Mono out Mix (2)
LOUT2 volume
ROUT2 volume
MONOOUT volume
Input boost mixer (1)
Input boost mixer (2)
Bypass (1)
Bypass (2)
Pwr Mgmt (3)
Additional Control (4)
Class D Control (1)
Reserved
Class D Control (3)
PLL N
PLL K 1
PLL K 2
PLL K 3
Bit[8]
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
Bit[0]
IPVU
LINMUTE
LIZC
LINVOL[5:0]
IPVU
RINMUTE
RIZC
RINVOL[5:0]
OUT1VU
LO1ZC
LOUT1VOL[6:0]
OUT1VU
RO1ZC
ROUT1VOL[6:0]
0
0
0
DACDIV[2:0]
SYSCLKDIV[1:0]
CLKSEL
0
DACDIV2
0
0
0
DACMU
DEEMPH[1:0]
0
0
0
DACPOL[1:0]
0
DACSMM
DACMR DACSLOPE
0
0
BCLKINV
MS
DLRSWAP
LRP
WL[1:0]
FORMAT[1:0]
DCLKDIV[2:0]
0
0
BCLKDIV[3:0]
0
0
ALRCGPIO
WL8
DACCOMP[1:0]
0
0
0
DACVU
LDACVOL[7:0]
DACVU
RDACVOL[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
writing to this register resets all registers to their default state
0
0
3DUC
3DLC
3DDEPTH[3:0]
3DEN
0
0
1
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
1
1
0
0
0
0
1
1
TSDEN
VSEL[1:0]
0
DMONOMIX
0
0
TOCLKSEL
TOEN
0
0
HPSWEN
HPSWPOL
0
TRIS
0
0
0
VMIDSEL[1:0]
VREF
AINL
AINR
0
0
MICB
DIGENB
DACL
DACR
LOUT1
ROUT1
SPKL
SPKR
0
OUT3
PLL_EN
0
0
VROI
0
0
OUT3CAP
0
0
0
0
POBCTRL
0
0
BUFDCOPEN
BUFIOEN
SOFT_ST
0
HPSTBY
0
0
DISOP
DRES[1:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LMN1
LMP3
LMP2
LMICBOOST[1:0]
LMIC2B
0
0
0
RMN1
RMP3
RMP2
RMICBOOST[1:0]
RMIC2B
0
0
0
LD2LO
LI2LO
LI2LOVOL[2:0]
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
0
1
0
0
0
0
RD2RO
RI2RO
RI2ROVOL[2:0]
0
0
0
0
0
L2MO
0
0
0
0
0
0
0
0
R2MO
0
0
0
0
0
0
0
SPKVU
SPKLZC
SPKLVOL[6:0]
SPKVU
SPKRZC
SPKRVOL[6:0]
0
0
MOUTVOL
0
0
0
0
0
0
0
0
LIN3BOOST[2:0]
LIN2BOOST[2:0]
0
0
0
RIN3BOOST[2:0]
RIN2BOOST[2:0]
0
0
LB2LO
LB2LOVOL[2:0]
0
0
0
0
0
RB2RO
RB2ROVOL[2:0]
0
0
0
0
0
0
0
LMIC
RMIC
LOMIX
ROMIX
0
0
0
GPIOPOL
GPIOSEL[2:0]
HPSEL[1:0]
TSENSEN
MBSEL
0
SPK_OP_EN[1:0]
1
1
0
1
1
1
0
0
1
0
0
1
1
0
1
0
1
0
DCGAIN[2:0]
ACGAIN[2:0]
OPCLKDIV[2:0]
SDM
PLLRESCALE
PLLN[3:0]
0
PLLK[23:16]
0
PLLK[15:8]
0
PLLK[7:0]
default
0_1001_0111
0_1001_0111
0_0000_0000
0_0000_0000
0_0000_0000
0_0000_1000
0_0000_0000
0_0000_1010
1_1100_0000
0_0000_0000
0_1111_1111
0_1111_1111
0_0000_0000
0_0000_0000
0_0000_0000
not reset
0_0000_0000
0_0111_1011
1_0000_0000
0_0011_0010
0_0000_0000
0_1100_0011
0_1100_0011
1_1100_0000
0_0000_0000
0_0000_0000
0_0000_0000
0_0000_0000
0_0000_0000
0_0000_0000
0_0000_0000
0_0000_0000
1_0000_0000
1_0000_0000
0_0101_0000
0_0101_0000
0_0101_0000
0_0101_0000
0_0000_0000
0_0000_0000
0_0000_0000
0_0000_0000
0_0100_0000
0_0000_0000
0_0000_0000
0_0101_0000
0_0101_0000
0_0000_0000
0_0000_0010
0_0011_0111
0_0100_1101
0_1000_0000
0_0000_1000
0_0011_0001
0_0010_0110
0_1110_1001
w
PD, November 2011, Rev 4.1
59
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