WM8960 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8960' PDF : 91 Pages View PDF
WM8960
Production Data
When DC blocking capacitors are used, then their capacitance and the load resistance together
determine the lower cut-off frequency, fc. Increasing the capacitance lowers fc, improving the bass
response. Smaller capacitance values will diminish the bass response. Assuming a 32 load and C1,
C2 = 100F:
fc = 1 / 2 RLC1 = 1 / (2 x 32 x 100F) = 50 Hz
In the DC coupled configuration, the headphone “ground” is connected to the OUT3 pin, which must
be enabled by setting OUT3 = 1 and muted by setting L2MO=0 and R2MO=0. As the OUT3 pin
produces a DC voltage of AVDD/2 (=VREF), there is no DC offset between HP_L/HP_R and OUT3,
and therefore no DC blocking capacitors are required. This saves space and material cost in portable
applications.
It is recommended to connect the DC coupled headphone outputs only to headphones, and not to the
line input of another device. Although the built-in short circuit protection will prevent any damage to
the headphone outputs, such a connection may be noisy, and may not function properly if the other
device is grounded.
CLASS D SPEAKER OUTPUTS
The class D speaker outputs SPK_LN/SPK_LP and SPK_RN/SPK_RP can drive 1W into 8 BTL
speakers. Class D outputs reduce power consumption and maximise efficiency by reducing power
dissipated in the output drivers, delivering most of the power directly to the load. This is achieved by
pulse width modulation (PWM) of a high frequency square wave, allowing the audio signal level to be
set by controlling the pulse width. The frequency of the output waveform is controlled by DCLKDIV,
and is derived from SYSCLK.
When the speakers are close to the device (typically less than about 100mm), the internal filtering
effects of the speaker can be used. Where signals are routed over longer distances, it is
recommended to use additional passive filtering, positioned close to the WM8960, to reduce EMI. See
"Applications Information" for more information on EMI reduction.
REGISTER
ADDRESS
R8 (08h)
Clocking (2)
BIT
LABEL
8:6 DCLKDIV
R49 (31h)
Class D
Control (1)
7:6 SPK_OP_EN
[1:0]
Table 28 Class D Control Registers
DEFAULT
DESCRIPTION
111
Controls clock division from
SYSCLK to generate suitable class
D clock.
000 = SYSCLK / 1.5
001 = SYSCLK / 2
010 = SYSCLK / 3
011 = SYSCLK / 4
100 = SYSCLK / 6
101 = SYSCLK / 8
110 = SYSCLK / 12
111 = SYSCLK / 16
00
Enable Class D Speaker Outputs
00 = Off
01 = Left speaker only
10 = Right speaker only
11 = Left and right speakers enabled
The class D outputs require a PWM switching clock, which is derived from SYSCLK. This clock
should not be altered or disabled while the class D outputs are enabled.
See "Clocking and Sample Rates" for more information.
w
PD, August 2013, Rev 4.2
42
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