WM8960 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'WM8960' PDF : 91 Pages View PDF
Production Data
WM8960
HEADPHONE JACK DETECT
The ADCLRC/GPIO1, LINPUT3/JD2 and RINPUT3/JD3 pins can be selected as headphone jack
detect inputs to automatically disable the speaker output and enable the headphone output e.g. when
a headphone is plugged into a jack socket. In this mode, enabled by setting HPSWEN, the
headphone detect input pin switches between headphone and speaker outputs (e.g. when the pin is
connected to a mechanical switch in the headphone socket to detect plug-in). The HPSEL[1:0] bits
select the input pin used for this function. The HPSWPOL bit reverses the pin’s polarity. Note that the
LOUT1, ROUT1, SPKL and SPKR bits in register 26 must also be set for headphone and speaker
output (see Table 29 and Table 30).
TOEN must also be set to enable the clock which is used for de-bouncing the jack detect input.
TOCLKSEL selects a fast or slow de-bounce period. Note that SYSCLK must be enabled to use this
function.
When using capless mode, the OUT3CAP bit should be enabled so that OUT3 is enabled/disabled at
the same time as HP_L and HP_R to prevent pop noise.
The debounced headphone detect signal can also be output to the ADCLRC/GPIO1 pin (See GPIO
section). This function is not available when using GPIO1 as an input or as ADCLRC.
When using the ADCLRC/GPIO1 pin as a headphone detect input, the ALRCGPIO register bit needs
to be set to 1. In this mode, DACLRC is used for both ADC and DAC frame clocks. (See GPIO
section for more information)
Note:
When LINPUT3 or RINPUT3 is used as the headphone detect input, the thresholds become CMOS
levels (0.3 AVDD / 0.7 AVDD).
HPSWEN
HPSWPOL
HEADPHONE
DETECT PIN
(LINPUT3/JD2,
RINPUT3/JD3 OR
ADCLRC/GPIO1)
0
X
X
0
X
X
0
X
X
0
X
X
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
Table 29 Headphone Jack Detect Operation
L/ROUT1
(AND OUT3 IN
CAPLESS MODE)
(REG. 26)
0
0
1
1
X
X
0
1
0
1
X
X
SPKL/R
(REG. 26)
0
1
0
1
0
1
X
X
X
X
0
1
HEADPHONE
ENABLED
(AND OUT3 IN
CAPLESS MODE)
SPEAKER
ENABLED
no
no
no
yes
yes
no
yes
yes
no
no
no
yes
no
no
yes
no
no
no
yes
no
no
no
no
yes
REGISTER
ADDRESS
R24 (18h)
Additional
Control (2)
BIT
LABEL
6
HPSWEN
5
HPSWPOL
DEFAULT
DESCRIPTION
0
Headphone Switch Enable
0 = Headphone switch disabled
1 = Headphone switch enabled
0
Headphone Switch Polarity
0 = HPDETECT high = headphone
1 = HPDETECT high = speaker
w
PD, August 2013, Rev 4.2
45
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