XR88C681CJ View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XR88C681CJ' PDF : 101 Pages View PDF
XR88C681
CLK
INTR
-S0
-S1
-S2
AD0 - AD7
CLK
-S0
-S1
-S2
DEN
DT/-R
-MRDC
-MWTC
-IORC
-IOWC
-INTA
ALE
8288 Bus Controller
-MEMR
-MEMW
-IOR
-IOW
D0 - D7
AD8 - AD15
8086 CPU
MN/-MX
D
Q
C
74LS373
D
Q
C
74LS373
A0 - A7
D8 - D15
A8 - A15
Figure 22. Schematic of the 8086 CPU Mode (Max Mode)
8086 C Interrupt Processing
If a peripheral component requires interrupt service from
the CPU, it will assert the CPU’s INTR input (by toggling it
high). Once the CPU has completed its current
instruction, it will assert the -INTA pin (if operating in the
“min” mode) or set the -S0, -S1, and -S2 pins to “0” (see
Table 15). In either case, the -IACK input of the peripheral
will be asserted. Once this happens, the interrupting
peripheral is expected to place an “interrupt vector” byte
on D0 - D7 of the data bus. The 8086 P will read this data
and multiply this value by the number 4 in order to
determine the location of the interrupt service routine in
memory. Since this “interrupt vector” is 8 bits wide, the
8086 P can accommodate up to 256 different interrupt
vectors (0 - 255). Additionally, since each vector is
multiplied by “4”, the user is expected to reserve the first
1K byte of memory for the Interrupt Service
Routines/Jump Table.
Figure 23 presents a schematic of the XR88C681
DUART interfacing to a “min” Mode 8086 CPU device.
Please note that the DUART has been configured to
operate in the Z-Mode. Therefore, the user must account
for the IEI input to the DUART device.
Rev. 2.11
49
Share Link: 
