XR88C681CJ View Datasheet(PDF) - Exar Corporation

Part Name

Description

MFG CO.

XR88C681CJ

CMOS Dual Channel UART (DUART)

Exar Corporation 

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XR88C681

AD0 - AD7

AD8 - AD15

HOLD

ALE

-DEN

DT/-R

-INTA

INTR

M/-IO

Vcc

-RD

MN/-MX

-WR

8086 CPU

D0 - D7

74LS373

D

Q

C

A4 - A7

A0 - A3

D8 - D15

74LS373

D

Q

C

A8 - A15

DAdedcoredsesr

pfrroiomrithyigdheevrice

D0 - D7

A0 - A3

-CS

-IACK

-INTR

IEI

-MEMR

-MEMW

-RD

-WR

XR88C681

Figure 23. Schematic of the XR88C681 DUART Device Interfacing to a

“Min” Mode 8086 CPU Device

D. TIMING CONTROL BLOCK

The Timing Control Block allows to the user to specify the

bit rates that he/she wishes to transmit and receive data at

each channel. The Timing Control Block consists of the

following elements:

D Oscillator Circuit

D Bit Rate Generator

D 16 bit Counter/Timer

D 4 - External Input Pins (to clock the Transmitters

and Receivers, directly)

D Two Clock Select Registers (32:1 MUXs)

Figure 24 presents a block diagram of the Timing Control

block for the XR88C681 device.

Rev. 2.11

50

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