XRT7302IQ80 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT7302IQ80' PDF : 77 Pages View PDF
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PIN DESCRIPTION
PIN #
42
SIGNAL NAME
REGR/
(RClkNV)
43
GND
44
VDD
45
EXClk2
46
RLOL2
47
LCV2
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT7302
REV. 1.1.0
TYPE
I
****
****
I
O
O
DESCRIPTION
Register Reset Input pin (Invert RxClk(n) Output - Select):
The exact function of this particular pin depends upon whether the XRT7302
device is operating in the "Host" Mode or in the "Hardware" Mode.
Host-Mode - Register Reset Input pin:
Setting this input pin "low" causes the XRT7302 device to reset the contents of
the Command Registers to their default settings. Additionally, it resets the
XRT7302 device to its "default" operating configuration.
NOTE: This pin is internally pulled "high".
Hardware Mode - Invert RxClk Output Select:
Setting this input pin "high" configures the Receive Section of both Channels
(within the XRT7302 device) to invert their "RxClk1 and RxClk2" clock output
signals.
Specifically, setting this pin "low" configures Channel 1 to output the recovered
data (via the RPOS1 and RNEG1 output pins) on the "rising" edge of the
RxClk1 output signal. This setting also configures Channel 2 to output the
recovered data (via the RPOS2 and RNEG2 output pins) on the "rising" edge
of the RxClk2 output signal.
Conversely, setting this input pin "high" configures Channel 1 to output the
recovered data (via the RPOS1 and RNEG1 output pins) on the "falling" edge
of the RxClk1 output signal. This setting also configures Channel 2 to output
the recovered data (via the RPOS2 and RNEG2 output pins on the "falling"
edge of the RxClk2 output signal
ExClk Reference GND
ExClk Reference VDD
External Reference Clock Input:
The user is expected to apply a 34.368 MHz clock signal (for E3 applications),
a 44.736 MHz clock signal (for DS3 applications), or a 51.84 MHz clock signal
(for SONET STS-1 applications).
NOTES:
1. It is permissible for one to use the same clock, which is also driving
the "TxClk" input pin.
2. It is permissible to operate Channel 2 at a different data rate than from
Channel 1.
Receive Loss of Lock Output Indicator - Channel 2
This output pin toggles "high" if the Receive Section of Channel 2 has
detected a "Loss of Lock" Condition. Channel 2 will declare an LOL (Loss of
Lock) Condition if the recovered clock frequency (at Channel 2) deviates from
the Reference Clock frequency (available at the ExClk input pin) by more than
0.5%.
Line Code Violation Indicator - Channel 2
Whenever the Receive Section of Channel 2 detects a Line Code Violation,
then it will pulse this output pin "high". This output pin will remain "low" at all
other times.
NOTE: The XRT7302 device will output an NRZ pulse via this output pin.
Hence, the user is advised to sample this output pin via the RxClk2 clock out-
put signal.
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