XRT79L71_10 View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT79L71_10' PDF : 609 Pages View PDF
XRT79L71
PRELIMINARY
1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE
REV. P2.0.0
FIGURE 11. ILLUSTRATION OF THE BEHAVIOR OF MICROPROCESSOR INTERFACE SIGNALS, DURING A "POWERPC
403" WRITE OPERATION
Microprocessor places “target” XRT79L71 samples
Address on A[14:0]
A[14:0] here
Microprocessor sets R/W*
To logic “Low” to denote
WRITE Operation
PCLK
CS*
R/W*
A[14:0]
D[7:0]
WE*
OE*
RDY
Target Address
Data to be Written
Microprocessor asserts WE* (RD*/DS*)
Here to initiate WRITE Operation
XRT79L71 samples
WE* Here
XRT79L71 responds by latching the
Contents of the Data Bus (into the
“target” address location), and by
Asserting RDY
WRITE Operation
Is terminated
Here
2.3.3 Interfacing the Microprocessor Interface to the MPC860 Microprocessor, when configured to
operate in the PowerPC 403 Mode
Figure 12 presents a schematic design on how we recommend that one interface the Microprocessor Interface
(of the XRT79L71, when it is configured to operate in the PowerPC 403 Mode) to an MPC860/8260 type of
Microprocessor.
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