XRT83SH38ES View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT83SH38ES' PDF : 78 Pages View PDF
XRT83SH38
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
TABLE 24: MICROPROCESSOR REGISTER 0X01H BIT DESCRIPTION
CHANNEL 0-7 (0X01H-0X71H)
BIT
NAME
FUNCTION
Register
Type
D1
JABW Jitter Bandwidth (E1 Mode Only, T1 is permanently set to 3Hz) R/W
The jitter bandwidth is a global setting that is applied to both the
receiver and transmitter jitter attenuator.
0 = 10Hz
1 = 1.5Hz
D0
FIFOS FIFO Depth Select
R/W
The FIFO depth select is used to configure the part for a 32-bit or
64-bit FIFO (within the jitter attenuator blocks). The delay of the
FIFO is equal to ½ the FIFO depth. This is a global setting that is
applied to both the receiver and transmitter FIFO.
0 = 32-Bit
1 = 64-Bit
REV. 1.0.7
Default
Value
(HW reset)
0
0
TABLE 25: MICROPROCESSOR REGISTER 0X02H BIT DESCRIPTION
CHANNEL 0-7 (0X02H-0X72H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
INVQRSS QRSS inversion
R/W
0
INVQRSS is used to invert the transmit QRSS pattern set by the
TxTEST[2:0] bits. By default, INVQRSS is disabled and the QRSS
will be transmitted with normal polarity.
0 = Disabled
1 = Enabled
D6
TxTEST2 Test Code Pattern
R/W
0
D5
TxTEST1 TxTEST[2:0] are used to select a diagnostic test pattern to the line
0
D4
TxTEST0 (transmit outputs).
0
0XX = No Pattern
100 = Tx QRSS
101 = Tx TAOS
110 = Reserved
111 = Reserved
55
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