XRT83SL314IB View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT83SL314IB' PDF : 83 Pages View PDF
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14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83SL314
REV. 1.0.1
TABLE 28: MICROPROCESSOR REGISTER 0X03H BIT DESCRIPTION
CHANNEL 0-13 (0X03H-0XD3H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D2
INSBPV Insert Bipolar Violation
R/W
0
When this bit transitions from a "0" to a "1", a bipolar violation will
be inserted in the transmitted QRSS/PRBS pattern. The state of
this bit will be sampled on the rising edge of TCLK. To ensure
proper operation, it is recommended to write a "0" to this bit before
writing a "1".
D1
INSBER Insert Bit Error
R/W
0
When this bit transitions from a "0" to a "1", a bit error will be
inserted in the transmitted QRSS/PRBS pattern. The state of this
bit will be sampled on the rising edge of TCLK. To ensure proper
operation, it is recommended to write a "0" to this bit before writing
a "1".
D0
Reserved This Register Bit is Not Used.
TABLE 29: MICROPROCESSOR REGISTER 0X04H BIT DESCRIPTION
CHANNEL 0-13 (0X04H-0XD4H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
EQFLAGE Equalizer Attenuation Flag Enable
0 = Masks the EQFLAG function
1 = Enables Interrupt Generation
R/W
0
D6
DMOIE Digital Monitor Output Interrupt Enable
0 = Masks the DMO function
1 = Enables Interrupt Generation
R/W
0
D5
FLSIE FIFO Limit Status Interrupt Enable
0 = Masks the FLS function
1 = Enables Interrupt Generation
R/W
0
D4
LCV/OFIE Line Code Violation / Counter Overflow Interrupt Enable
0 = Masks the LCV/OF function
1 = Enables Interrupt Generation
R/W
0
D3
NLCDIE Network Loop Code Detection Interrupt Enable
0 = Masks the NLCD function
1 = Enables Interrupt Generation
R/W
0
D2
AISIE Alarm Indication Signal Interrupt Enable
0 = Masks the AIS function
1 = Enables Interrupt Generation
R/W
0
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