XRT83SL314IB View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT83SL314IB' PDF : 83 Pages View PDF
XRT83SL314
REV. 1.0.1
xr
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
TABLE 29: MICROPROCESSOR REGISTER 0X04H BIT DESCRIPTION
CHANNEL 0-13 (0X04H-0XD4H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D1
RLOSIE Receiver Loss of Signal Interrupt Enable
0 = Masks the RLOS function
1 = Enables Interrupt Generation
R/W
0
D0
QRPDIE Quasi Random Signal Source Interrupt Enable
0 = Masks the QRPD function
1 = Enables Interrupt Generation
R/W
0
NOTE: The GIE bit in the global register 0xE0h must be set to "1" in addition to the individual register bits to enable the
interrupt pin.
TABLE 30: MICROPROCESSOR REGISTER 0X05H BIT DESCRIPTION
CHANNEL 0-13 (0X05H-0XD5H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
EQFLAG Equalizer Attenuation Flag
RO
0
The equalizer attenuation flag is always active regardless if the
interrupt generation is disabled. This bit indicates the EQFLAG
activity. An interrupt will not occur unless the EQFLAGE is set to
"1" in the channel register 0x04h and GIE is set to "1" in the global
register 0xE0h.
0 = No Alarm
1 = Equalizer Attenuation Flag is Set
D6
DMO Digital Monitor Output
RO
0
The digital monitor output is always active regardless if the inter-
rupt generation is disabled. This bit indicates the DMO activity. An
interrupt will not occur unless the DMOIE is set to "1" in the chan-
nel register 0x04h and GIE is set to "1" in the global register
0xE0h.
0 = No Alarm
1 = Transmit output driver has failures
D5
FLS FIFO Limit Status
RO
0
The FIFO limit status is always active regardless if the interrupt
generation is disabled. This bit indicates whether the RD/WR
pointers are within 3-Bits. An interrupt will not occur unless the
FLSIE is set to "1" in the channel register 0x04h and GIE is set to
"1" in the global register 0xE0h.
0 = No Alarm
1 = RD/WR FIFO pointers are within ±3-Bits
57
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