XRT91L81IB View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L81IB' PDF : 40 Pages View PDF
XRT91L81
2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
REV. P1.0.3
PRELIMINARY
3.7 Loop Timing and clock control
Two types of loop timing are possible in the XRT91L81. In the regular loop timing mode (without an external
VCXO), the loop timing is controlled by the LPTIME_NO_JA pin. This mode is selected by asserting the
LPTIME_NO_JA signal to a high level. When the loop timing mode is activated the external reference clock to
the input of the CMU is replaced with the 1/16th or the 1/32nd of the high-speed recovered receive clock from
the CDR. Under this condition both the transmit and receive sections are synchronized to the recovered
receive clock. The normal looptime mode directly locks the CMU to the recovered receive clock with no
external de-jittering.
In cases when the jitter of the recovered receive clock does not satisfy the strict ITU and Bellcore jitter
generation requirements, an external VCXO-based PLL can be used to clean up the jitter of the recovered
receive clock. In this case the VCXO_SEL pin should be set high. By doing so, the CMU receives its reference
clock signal from an external VCXO connected to the VCXO_INP/N inputs. The LPTIME_JA pin must also be
set high in order to select the recovered receive clock as the reference source for the de-jitter PLL. In this state,
the VCXO will be phase locked to the recovered receive clock through a narrowband loop filter. The use of the
on-chip phase/frequency detector with charge pump and an external VCXO to remove the transmit jitter due to
jitter in the recovered clock is shown in Figure 10. The on-chip phase/frequency detector can also be used to
remove the jitter from a noisy reference signal that is applied to the REFCLKP/N inputs. In this case the
LPTIME_NO_JA pin should be set "Low", the VCXO_SEL set "High", and the LPTIME_JA pin set "Low". In this
configuration, the REFCLKP/N signal is used as the reference to the de-jitter PLL and the de-jittered output of
the phase locked VCXO is used as the timing reference to the CMU. Table 5 provides configuration for
selecting the loop timing and reference de-jitter modes.
TABLE 5: LOOP TIMING AND REFERENCE DE-JITTER CONFIGURATIONS
VCXO_SEL
LPTIME_JA
LPTIME_NO_JA
ACTION
0
0
0
Normal mode
0
0
1
Loop timing without de-jitter
1
0
0
Reference de-jitter
1
1
0
Loop timing with de-jitter
20
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