XRT91L81IB View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L81IB' PDF : 40 Pages View PDF
PRELIMINARY
XRT91L81
2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
REV. P1.0.3
6.0 REGISTER MAP AND BIT DESCRIPTIONS
TABLE 6: MICROPROCESSOR REGISTER MAP
REG ADDR TYPE
D7
D6
D5
D4
D3
D2
D1
D0
Channel 0 Control Register (0x00h - 0x05h)
0
0x00
1
0x01
2
0x02
3
0x03
4
0x04
5
0x05
0x06 - 0x3D
R/W Reserved
Reserved
RUR Reserved
Reserved
RO Reserved
Reserved
R/W TXO2DIS REFREQSEL
R/W Reserved POLARITY
R/W Reserved
Reserved
R/W Reserved
Reserved
Reserved
Reserved
TXO2SEL
LOOPTM
Reserved
VCXOIE
VCXOIS
VCXOID
LOOPBW
LPTIMJADIS
Reserved
LOSIE
CDRIE
CMUIE
LOSIS
CDRIS
CMUIS
LOSID
CDRID
CMUID
VCXOSEL TRITXCLK016 AUTORST
DISRD
TRIRXD
RXSEL
Reserved
DLOOP
RLOOPS
FIFOIE
FIFOIS
FIFOID
FIFORST
VCXOLKEN
RLOOPP
62 0x3E RO Device ID (See Bit Description)
63 0x3F RO Revision ID (See Bit Description)
TABLE 7: MICROPROCESSOR REGISTER BIT DESCRIPTION
CHANNEL 0 CONTROL REGISTER (0X00H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved This Register Bit is Not Used
X
X
D6
Reserved This Register Bit is Not Used
X
X
D5
Reserved This Register Bit is Not Used
X
X
D4
VCXOIE Voltage Controlled External OscillatorLock Interrupt Enable
R/W
0
"0" = Masks the VCXO interrupt generation
"1" = Enables Interrupt generation
D3
LOSIE Loss of Signal Interrupt Enable
"0" = Masks the LOS interrupt generation
"1" = Enables Interrupt generation
R/W
0
D2
CDRIE Clock and Data Recovery Lock Interrupt Enable
"0" = Masks the CDR lock interrupt generation
"1" = Enables Interrupt generation
R/W
0
D1
CMUIE Clock Multiplier Unit Lock Interrupt Enable
"0" = Masks the CMU lock interrupt generation
"1" = Enables Interrupt generation
R/W
0
D0
FIFOIE FIFO Overflow Interrupt Enable
"0" = Masks the FIFO interrupt generation
"1" = Enables Interrupt generation
R/W
0
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