XRT91L81IB View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L81IB' PDF : 40 Pages View PDF
PRELIMINARY
XRT91L81
2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
REV. P1.0.3
CHANNEL 0 CONTROL REGISTER (0X02H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D3
LOSID Loss of Signal Detection
RO
0
The LOSID indicates the LOS activity. An interrupt will not occur
unless the RLOSIE is set to "1" in the channel register 0x00h.
"0" = No Alarm
"1" = A LOS condition is present
D2
CDRID Clock and Data Recovery Lock Detection
RO
0
The CDRID is used to indicate that the CDR is locked. An interrupt
will not occur unless the CDRIE is set to "1" in the channel register
0x00h.
"0" = No Alarm
"1" = A LOS condition is present
D1
CMUID Clock Multiplier Unit Lock Detection
RO
0
The CMUID is used to indicate that the CMU is locked. An inter-
rupt will not occur unless the CMUIE is set to "1" in the channel
register 0x00h.
"0" = No Alarm
"1" = A LOS condition is present
D0
FIFOID FIFO Overflow Detection
RO
0
The FIFOID indicates that the FIFO has experienced an overflow
condition. An interrupt will not occur unless the FIFOIE is set to "1"
in the channel register 0x00h.
"0" = No Alarm
"1" = A LOS condition is present
TABLE 10: MICROPROCESSOR REGISTER BIT DESCRIPTION
CHANNEL 0 CONTROL REGISTER (0X03H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
TXO2DIS Secondary Transmit Serial Output Disable
R/W
0
This bit is used to disable the secondary transmit serial output. By
default, the secondary transmit signal is enabled.
"0" = Enabled
"1" = Disabled
D6 REFREQSEL Input Reference Frequency Select
This bit is used to select the input clock reference.
"0" = 77.76/83.3 MHz
"1"= 155.52/166 MHz
R/W
0
31
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