XRT91L81IB View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L81IB' PDF : 40 Pages View PDF
XRT91L81
2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
REV. P1.0.3
PRELIMINARY
TABLE 10: MICROPROCESSOR REGISTER BIT DESCRIPTION
CHANNEL 0 CONTROL REGISTER (0X03H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D5
TXO2SEL Secondary Transmit Serial Output Select
R/W
0
This bit is used to select between serial data and a reference clock
for the secondary transmit serial output.
"0" = 2.488Gbit/s Serial Output Data
"1" = Transmit Output Clock (2.488/2.666 GHz)
D4
LOOPBW CMU Loop Band Width Select
R/W
0
This bit is used to select the bandwidth of the clock multiplier unit
of the transmit path to a narrow or wide band.
"0" = Narrow Band (1x)
"1" = Wide Band (4x)
D3
VCXOSEL VCXO De-Jitter Select
R/W
0
This bit selects either the normal REFCLK or the de-jitter VCXO as
a reference clock.
"0" = Normal REFCLK Mode
"1" = De-Jitter VCXO Mode
D2 TRITXCLKO16 Auxillary Output Clock Tri-State
This bit is used to tri-state the auxillary clock.
"0" = TXCLKO16 Enabled
"1" = TXCLKO16 Tri-State
R/W
0
D1
AUTORST Automatic FIFO Overflow Reset
R/W
0
If this bit is set to "1", the OC-48 transceiver will automatically flush
the FIFO upon an overflow condition. Upon power-up, the FIFO
should be manually reset by setting FIFO_RST to "1" for 10 cycles
of TXCLK.
"0" = Manual FIFO reset required for overflow conditions
"1" = Automatically resets FIFO upon overflow detection
D0
FIFORST Manual FIFO Reset
R/W
0
FIFORST should be set to "1" for 10 cycles of TXCLK during
power-up in order to flush out the FIFO. Upon an interrupt indica-
tion that the FIFO has an overflow condition, this bit is used to
reset or flush out the FIFO.
NOTE: To automaically reset the FIFO, see the AUTORST bit.
32
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