XRT91L81IB View Datasheet(PDF) - Exar Corporation
Part Name
Description
MFG CO.
'XRT91L81IB' PDF : 40 Pages View PDF
PRELIMINARY
XRT91L81
2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
REV. P1.0.3
TABLE 11: MICROPROCESSOR REGISTER BIT DESCRIPTION
CHANNEL 0 CONTROL REGISTER (0X04H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved This Register Bit is Not Used
X
X
D6
POLARITY Polarity for LOS Input Select
R/W
0
LOSEXT and POLARITY bits will be Exlussive NORed
internally to generate the correct polarity.
D5 LOOPTM_JA Loop Timing With JA
R/W
0
The LOOPTM_JA bit must be set to "1" in order to select the recov-
ered receive clock as the reference source for the de-jitter PLL.
"0" = Disabled
"1" = Enabled
D4 LPTIMJADIS Loop Timing With No JA
R/W
0
When the loop timing mode is activated the external reference
clock to the input of the CMU is replaced with the 1/16th or the 1/
32nd of the high-speed recovered receive clock from the CDR.
"0" = Disabled
"1" = Loop timing Activated
D3
DISRD
Receive Output Disable Upon LOS
R/W
0
If this bit is set to "1", the receive output data will automically pull
"Low" when a LOS condition occurs.
"0" = Disabled
"1" = Mute Data Upon LOS
D2
TRIRXD Receive Output Tri-State
R/W
0
This bit is used to control the activity of the 4-bit parallel receive
output bus and its reference clock.
"0" = Normal Mode
"1" = Tri-State RXDP/N[3:0] and RXCLK
D1
RXSEL
Receive Serial Input Select
R/W
0
This bit is used to select the Receive Serial Data Input from the pri-
mary or secondary inputs.
"0" = RXI0
"1" = RXI1
D0
VCXOLKEN De-Jitter PLL Lock Detect Enable
This bit enables the VCXO lock detect Pin N8 to be active.
"0" = VCXO_LOCK disabled
"1" = VCXO_LOCK enabled
R/W
0
33
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