XWM8739SEDS/V View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'XWM8739SEDS/V' PDF : 37 Pages View PDF
WM8739
Production Data
The exact sample rates supported for all combinations are defined by the relationships in Table 11
below.
TARGET
SAMPLING
RATE
kHz
8
ACTUAL SAMPLING RATE
BOSR=0
BOSR=1
( 250fs)
(272fs)
kHz
kHz
8
8.021
12MHz/(250 x 48/8)
12MHz/(272 x 11/2)
32
32
not available
44.1
12MHz/(250 x 48/32)
not available
44.117
12MHz/272
48
48
not available
88.2
12MHz/250
not available
88.235
12MHz/136
96
96
not available
12MHz/125
Table 11 USB Mode Actual Sample Rates
ACTIVATING DSP AND DIGITAL AUDIO INTERFACE
To prevent any communication problems from arising across the Digital Audio Interface the Audio
Interface is disabled (tristate). Once the Audio Interface and the Sampling Control has been
programmed it is activated by setting the ACTIVE bit under Software Control.
REGISTER
ADDRESS
0001001
Active Control
BIT
LABEL
DEFAULT
0
ACTIVE 0
Table 12 Activating DSP and Digital Audio Interface
DESCRIPTION
Activate Interface
1 = Active
0 = Inactive
It is recommended that between changing any content of Digital Audio Interface or Sampling Control
Register that the active bit is reset then set.
SOFTWARE CONTROL INTERFACE
The software control interface may be operated using either a 3-wire or 2-wire MPU interface.
Selection of interface format is achieved by setting the state of the MODE pin.
In 3-wire mode, SDIN is used for the program data, SCLK is used to clock in the program data and
CSB is used to latch in the program data. In 2-wire mode, SDIN is used for serial data and SCLK is
used for the serial clock. In 2-wire mode, the state of the CSB pin allows the user to select one of two
addresses.
SELECTION OF SERIAL CONTROL MODE
The serial control interface may be selected to operate in either 2 or 3-wire mode. This is achieved
by setting the state of the MODE pin.
MODE
INTERFACE FORMAT
0
2 wire
1
3 wire
Table 13 Control Interface Mode Selection
3-WIRE SERIAL CONTROL MODE
The WM8739 can be controlled using a 3-wire serial interface. SDIN is used for the program data,
SCLK is used to clock in the program data and CSB is used to latch in the program data. The 3-wire
interface protocol is shown in Figure 19.
w
PD, Rev 4.2, July 2008
25
Share Link: 
