XWM8739SEDS/V View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'XWM8739SEDS/V' PDF : 37 Pages View PDF
WM8739
Production Data
CSB
SCLK
SDIN
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Figure 19 3-Wire Serial Interface
Notes:
1. B[15:9] are Control Address Bits
2. B[8:0] are Control Data Bits
2-WIRE SERIAL CONTROL MODE
The WM8739 supports a 2-wire MPU serial interface. The device operates as a slave device only.
The WM8739 has one of two slave addresses that are selected by setting the state of pin 20, (CSB).
SDIN
R ADDR
R/W
ACK
DATA B15-8 ACK
DATA B7-0
ACK
SCLK
START
Figure 20 2-Wire Serial Interface
Notes:
1. B[15:9] are Control Address Bits
2. B[8:0] are Control Data Bits
STOP
CSB STATE
ADDRESS
(DEFAULT = LOW)
0
0011010
1
0011011
Table 14 2-Wire MPU Interface Address Selection
To control the WM8739 on the 2-wire bus the master control device must initiate a data transfer by
establishing a start condition, defined by a high to low transition on SDIN while SCLK remains high.
This indicates that an address and data transfer will follow. All peripherals on the 2-wire bus respond
to the start condition and shift in the next eight bits (7-bit address + R/W bit). The transfer is MSB
first. The 7-bit address consists of a 6-bit base address + a single programmable bit to select one of
two available addresses for this device (see Table 14). If the correct address is received and the R/W
bit is ‘0’, indicating a write, then the WM8739 will respond by pulling SDIN low on the next clock pulse
(ACK). The WM8739 is a write only device and will only respond to the R/W bit indicating a write. If
the address is not recognised the device will return to the idle condition and wait for a new start
condition and valid address.
Once the WM8739 has acknowledged a correct address, the controller will send eight data bits (bits
B[15]-B[8]). WM8739 will then acknowledge the sent data by pulling SDIN low for one clock pulse.
The controller will then send the remaining eight data bits (bits B[7]-B[0]) and the WM8739 will then
acknowledge again by pulling SDIN low.
A stop condition is defined when there is a low to high transition on SDIN while SCLK is high. If a
start or stop condition is detected out of sequence at any point in the data transfer then the device
will jump to the idle condition.
w
PD, Rev 4.2, July 2008
26
Share Link: 
