Z86E72/E73
OTP IR Microcontrollers
COUNTER/TIMER REGISTER DESCRIPTION (Continued)
SMR2(F) %0D: Stop-Mode Recovery Register 2.
Field
Bit Position
Reserved
7-------
Recovery Level
-6------
W
Reserved
--5-----
Source
---432--
W
Reserved
------10
Note: * Indicates the value upon Power-On Reset.
Value
0
0*
1
0
000*
001
010
011
100
101
110
111
00
Description
Reserved (Must be 0)
Low
High
Reserved (Must be 0)
A. POR Only
B. NAND of P23-P20
C. NAND or P27-P20
D. NOR of P33-P31
E. NAND of P33-P31
F. NOR of P33-P31, P00,P07
G. NAND of P33-P31,P00,P07
H. NAND of P33-P31,P22-P20
Reserved (Must be 0)
Counter/Timer Functional Blocks
P31
MUX
P20
CTR1 D5,D4
Glitch
Filter
Edge
Detector
Pos Edge
Neg Edge
CTR1 D6
CTR1 D3,D2
Figure 25. Glitch Filter Circuitry
1-36
PRELIMINARY
DS96LVO1100