Z86E7316FSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z86E7316FSC' PDF : 74 Pages View PDF
Z86E72/E73
OTP IR Microcontrollers
COUNTER/TIMER REGISTER DESCRIPTION (Continued)
SMR2 (0F) DH
D7 D6 D5 D4 D3 D2 D1 D0
Note: If used in conjunction with SMR,
either of the two specified events will
cause a Stop-Mode Recovery.
*Default Setting After Reset
Reserved (Must be 0)
Reserved (Must be 0)
Stop-Mode Recovery Source 2
000 POR only*
001 NAND P20, P21, P22, P23
010 NAND P20, P21, P22, P23, P24, P25, P26, P27
011 NOR P31, P32, P33
100 NAND P31, P32, P33
101 NOR P31, P32, P33, P00, P07
110 NAND P31, P32, P33, P00, P07
111 NAND P31, P32, P33, P20, P21, P22
Reserved
(Must be 0)
Recovery Level
0 Low*
1 High
Reserved (Must be 0)
Figure 42. Stop-Mode Recovery Register 2
((0F) DH: D2-D4, D6 Write Only)
Watch-Dog Timer Mode Register (WDTMR). The WDT
is a retriggerable one-shot timer that resets the Z8 if it
reaches its terminal count. The WDT must initially be en-
abled by executing the WDT instruction and refreshed on
subsequent executions of the WDT instruction. The WDT
circuit is driven by an on-board RC oscillator or external
oscillator from the XTAL1 pin. The WDT instruction affects
the Zero (Z), Sign (S), and Overflow (V) flags.
The POR clock source is selected with bit 4 of the WDT
register. Bit 0 and 1 control a tap circuit that determines the
time-out period. Bit 2 determines whether the WDT is ac-
tive during HALT and Bit 3 determines WDT activity during
STOP. Bits 5 through 7 are reserved (Figure 48).
This register is accessible only during the first 64 proces-
sor cycles (128 XTAL clocks) from the execution of the first
instruction after Power-On-Reset, Watch-Dog Reset, or a
Stop-Mode Recovery (Figure 40). After this point, the reg-
ister cannot be modified by any means, intentional or oth-
erwise. The WDTMR cannot be read and is located in
Bank F of the Expanded Register Group at address loca-
tion 0FH. It is organized as follows:
1-52
PRELIMINARY
DS96LVO1100
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