Z86E72/E73
OTP IR Microcontrollers
COUNTER/TIMER REGISTER DESCRIPTION (Continued)
/RESET
5 Clock
Filter
* /CLR 2
CLK
18 Clock RESET
Generator
RESET
CK Source
Select
(WDTMR)
XTAL
VDD
VBO/VLV
2V REF.
M
U
INTERNAL
X
RC
OSC.
Low Operating
+ Voltage Det.
-
WDT TAP SELECT
POR WDT1 2
3
4
CLK *CLR1 WDT/POR Counter Chain
WDT
From Stop
Mode
Recovery
Source
12 ns Glitch Filter
Stop Delay
Select (SMR)
* /CLR1 and /CLR2 enable the WDT/POR and
18 Clock Reset timers upon a Low to High input translation.
VCC
Figure 44. Resets and WDT
Internal
RESET
Active
High
1-54
PRELIMINARY
DS96LVO1100