Z86E7316FSC View Datasheet(PDF) - Zilog
Part Name
Description
MFG CO.
'Z86E7316FSC' PDF : 74 Pages View PDF
Z86E72/E73
OTP IR Microcontrollers
WDTMR (0F) FH
D7 D6 D5 D4 D3 D2 D1 D0
1
* Default Setting After Reset
WDT TAP
00
01 *
10
11
INT RC OSC External Clock
5 ms
256 TpC
10 ms
512 TpC
20 ms
1024 TpC
80 ms
4096 TpC
WDT During HALT
0 OFF
1 ON *
WDT During STOP
0 OFF
1 ON *
XTAL1/INT RC Select for WDT
0 On-Board RC *
1 XTAL
Reserved (Must be 0)
Figure 43. Watch-Dog Timer Mode Register
(Write Only)
WDT Time Select (D0, D1). Selects the WDT time period.
It is configured as shown in Table 13.
Table 9. WDT Time Select
D1
D0
0
0
0
1
1
0
1
1
Notes:
TpC = XTAL clock cycle
The default on reset is 10 ms
Time-Out of
Internal RC Time-Out of
OSC XTAL Clock
5 ms min
10 ms mi
20 ms mi
80 ms mi
256 TpC
512 TpC
1024 TpC
4096 TpC
WDTMR During STOP (D3). This bit determines whether
or not the WDT is active during STOP mode. Since the
XTAL clock is stopped during STOP mode, the on-board
RC has to be selected as the clock source to the
WDT/POR counter. A 1 indicates active during STOP. The
default is 1.
Clock Source for WDT (D4). This bit determines which
oscillator source is used to clock the internal POR and
WDT counter chain. If the bit is a 1, the internal RC oscil-
lator is bypassed and the POR and WDT clock source is
driven from the external pin, XTAL1. The default configu-
ration of this bit is 0, which selects the RC oscillator.
WDTMR During HALT (D2). This bit determines whether
or not the WDT is active during HALT mode. A 1 indicates
active during HALT. The default is 1.
DS96LVO1100
PRELIMINARY
1-53
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