EiceDRIVERTM SIL
1EDI2004AS
Functional Description
a)
tPULSE < tTTOFF + tAMCDel + ½ . tSSOSC
Input Pulse
tPDON
tTTOFF
2 . tSSOSC + tAMCDel
TTOFF Plateau
tAMCDel
tTTOFF
Output Pulse
b)
tPULSE > tTTOFF + tAMCDel + ½ . tSSOSC
Input Pulse
tPDON
tTTOFF
tAMCDel
tPDOFF
tAMCDel
tTTOFF
Output Pulse
Figure 13 TTOFF: Principle of Operation
tPULSE
Pulse Suppressor
In order to increase the device’s robustness against external disturbances, a pulse suppressor can be enabled
by setting bit SCFG.PSEN. Register SRTTOF shall also programmed with a value higher than 2H. When a PWM
turn-on sequence occurs, the activation of the output stage is delayed by the programmed TTOFF number of
cycles, as for a normal TTOFF sequence. However, the PWM command received by the secondary chip signal
is internally sampled at every SSOSC cycle before the actual turn-on command is executed by the output
stage. If at least one of the sampling point does not detect a high level, the turn-on sequence is aborted and
the device is not switched on.
In case a valid PWM ON command is detected by the secondary side after the decision point the previous
sequence has been aborted, a new turn-on sequence is initiated.
One of the consequence of activating the pulse suppressor is that all PWM pulses shorter than the
programmed TTOFF plateau time are filtered out (Figure 14).
Data Sheet
39
Rev. 2.0
2019-01-16