28F256L18 View Datasheet(PDF) - Numonyx -> Micron
Part Name
Description
MFG CO.
'28F256L18' PDF : 106 Pages View PDF
Numonyx™ StrataFlash® Wireless Memory (L18)
Figure 23: Reset Operation Waveforms
(A) Reset during
read mode
VIH
RST# [P]
VIL
(B) Reset during
program or block erase
P1 ≤ P2
(C) Reset during
program or block erase
P1 ≥ P2
VIH
RST# [P]
VIL
V
IH
RST# [P]
VIL
(D) VCC Power-up to
RST# high
VCC
VCC
0V
P1
R5
Abort
P2
R5
Complete
Abort
P2
R5
Complete
P3
8.3
8.4
Power Supply Decoupling
Flash memory devices require careful power supply decoupling. Three basic power
supply current considerations are: 1) standby current levels; 2) active current levels;
and 3) transient peaks produced when CE# and OE# are asserted and deasserted.
When the device is accessed, many internal conditions change. Circuits within the
device enable charge-pumps, and internal logic states change at high speed. All of
these internal activities produce transient signals. Transient current magnitudes depend
on the device outputs’ capacitive and inductive loading. Two-line control and correct
decoupling capacitor selection suppress transient voltage peaks.
Because Numonyx Multi-Level Cell (MLC) flash memory devices draw their power from
VCC, VPP, and VCCQ, each power connection should have a 0.1 µF ceramic capacitor
connected to a corresponding ground connection. High-frequency, inherently low-
inductance capacitors should be placed as close as possible to package leads.
Additionally, for every eight devices used in the system, a 4.7 µF electrolytic capacitor
should be placed between power and ground close to the devices. The bulk capacitor is
meant to overcome voltage droop caused by PCB trace inductance.
Automatic Power Saving
Automatic Power Saving (APS) provides low power operation during a read’s active
state. ICCAPS is the average current measured over any 5 ms time interval, 5 μs after
CE# is deasserted. During APS, average current is measured over the same time
interval 5 μs after the following events happen: (1) there is no internal read, program
or erase operations cease; (2) CE# is asserted; (3) the address lines are quiescent and
at VSSQ or VCCQ. OE# may also be driven during APS.
November 2007
251902-12
Datasheet
41
Share Link: 
