28F256L18 View Datasheet(PDF) - Numonyx -> Micron
Part Name
Description
MFG CO.
'28F256L18' PDF : 106 Pages View PDF
Numonyx™ StrataFlash® Wireless Memory (L18)
10.2.1
Burst Suspend
The Burst Suspend feature of the device can reduce or eliminate the initial access
latency incurred when system software needs to suspend a burst sequence that is in
progress in order to retrieve data from another device on the same system bus. The
system processor can resume the burst sequence later. Burst suspend provides
maximum benefit in non-cache systems.
Burst accesses can be suspended during the initial access latency (before data is
received) or after the device has output data. When a burst access is suspended,
internal array sensing continues and any previously latched internal data is retained. A
burst sequence can be suspended and resumed without limit as long as device
operation conditions are met.
Burst Suspend occurs when CE# is asserted, the current address has been latched
(either ADV# rising edge or valid CLK edge), CLK is halted, and OE# is deasserted. CLK
can be halted when it is at VIH or VIL. WAIT is in High-Z during OE# deassertion.
To resume the burst access, OE# is reasserted, and CLK is restarted. Subsequent CLK
edges resume the burst sequence.
Within the device, CE# and OE# gate WAIT. Therefore, during Burst Suspend WAIT is
placed in high-impedance state when OE# is deasserted and resumed active when OE#
is re-asserted. See Figure 17, “Burst Suspend Timing” on page 34.
10.3
Read Configuration Register (RCR)
The RCR is used to select the read mode (synchronous or asynchronous), and it defines
the synchronous burst characteristics of the device. To modify RCR settings, use the
Configure Read Configuration Register command (see Section 9.2, “Device Commands”
on page 44).
RCR contents can be examined using the Read Device Identifier command, and then
reading from <partition base address> + 0x05 (see Section 15.2, “Read Device
Identifier” on page 74).
The RCR is shown in Table 22. The following sections describe each RCR bit.
Table 22: Read Configuration Register Description (Sheet 1 of 2)
Read Configuration Register (RCR)
Read
Mode
RM
15
Bit
15
14
13:11
RES
Latency Count
R
LC[2:0]
14 13 12 11
Name
Read Mode (RM)
Reserved (R)
Latency Count (LC[2:0])
WAIT Data WAIT Burst CLK
RES RES
Polarity Hold Delay Seq Edge
WP
DH WD
BS
CE
R
R
10
9
8
7
6
5
4
Description
0 = Synchronous burst-mode read
1 = Asynchronous page-mode read (default)
Reserved bits should be cleared (0)
010 =Code 2
011 =Code 3
100 =Code 4
101 =Code 5
110 =Code 6
111 =Code 7 (default)
(Other bit settings are reserved)
Burst
Wrap
BW
3
Burst Length
BL[2:0]
2
1
0
November 2007
251902-12
Datasheet
49
Share Link: 
