28F256L18 View Datasheet(PDF) - Numonyx -> Micron
Part Name
Description
MFG CO.
'28F256L18' PDF : 106 Pages View PDF
Numonyx™ StrataFlash® Wireless Memory (L18)
When returning from a reset (RST# deasserted), a minimum wait is required before the
initial read access outputs valid data. Also, a minimum delay is required after a reset
before a write cycle can be initiated. After this wake-up interval passes, normal
operation is restored. See Section 7.0, “AC Characteristics” on page 26 for details
about signal-timing.
9.2
Device Commands
Device operations are initiated by writing specific device commands to the Command
User Interface (CUI). See Table 20, “Command Bus Cycles” on page 44.
Several commands are used to modify array data including Word Program and Block
Erase commands. Writing either command to the CUI initiates a sequence of internally-
timed functions that culminate in the completion of the requested task. However, the
operation can be aborted by either asserting RST# or by issuing an appropriate
suspend command.
Table 20: Command Bus Cycles (Sheet 1 of 2)
Mode
Read
Program
Erase
Suspend
Block
Locking/
Unlocking
Command
Bus
Cycles
First Bus Cycle
Oper Addr1 Data2
Second Bus Cycle
Oper Addr1 Data2
Read Array
1
Write PnA 0xFF
Read Device Identifier
≥ 2 Write PnA 0x90 Read PBA+IA
ID
CFI Query
≥ 2 Write PnA 0x98 Read PnA+QA QD
Read Status Register
2
Write PnA 0x70 Read
PnA
SRD
Clear Status Register
1
Write
X
0x50
Word Program
Buffered Program3
0x40/
2
Write
WA
0x10 Write
WA
> 2 Write WA 0xE8 Write
WA
WD
N-1
Buffered Enhanced Factory Program (Buffered
EFP)4
>2
Write
WA
0x80 Write
WA
0xD0
Block Erase
2
Write BA 0x20 Write
BA
0xD0
Program/Erase Suspend
Program/Erase Resume
Lock Block
Unlock Block
Lock-down Block
1
Write
X
0xB0
1
Write
X
0xD0
2
Write BA 0x60 Write
BA
2
Write BA 0x60 Write
BA
2
Write BA 0x60 Write
BA
0x01
0xD0
0x2F
Datasheet
44
November 2007
251902-12
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