5962-9750701HXC View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'5962-9750701HXC' PDF : 44 Pages View PDF
AD14060/AD14060L
Pin
BMSBCD
TIMEXPy
CLKIN
RESET
TCK
TMS
TDI
TDO
TRST
EMU (O/D)
VDD
GND
Type
I/O/T2
O
I
I/A
I
I/S
I/S
O
I/A
O
P
G
Function
Boot Memory Select. Output: Used as chip select for boot EPROM devices (when EBOOTBCD = 1,
LBOOTBCD = 0). In a multiprocessor system, BMS is output by the bus master. Input: When low,
indicates that no booting will occur and that SHARC_B, C, D will begin executing instructions from
external memory. See table below. This input is a system configuration selection which should be
hardwired.
EBOOT LBOOT BMS
Booting Mode
1
0
Output EPROM (Connect BMS to EPROM chip select)
0
0
1 (Input) Host Processor
0
1
1 (Input) Link Port
0
0
0 (Input) No Booting. Processor executes from external memory.
0
1
0 (Input) Reserved
1
1
x (Input) Reserved
Timer Expired. (Individual TIMEXP from y = SHARC_A, SHARC_B, SHARC_C, SHARC_D) Asserted
for four cycles when the timer is enabled and TCOUNT decrements to zero.
Clock In. (Common to all SHARCs) External clock input to the AD14060/AD14060L. The instruction
cycle rate is equal to CLKIN. CLKIN may not be halted, changed, or operated below the minimum specified
frequency.
Module Reset. (Common to all SHARCs) Resets the AD14060/AD14060L to a known state. This input
must be asserted (low) at power-up.
Test Clock (JTAG). (Common to all SHARCs) Provides an asynchronous clock for JTAG boundary
scan.
Test Mode Select (JTAG). (Common to all SHARCs) Used to control the test state machine. TMS has
a 20 kΩ internal pull-up resistor.
Test Data Input (JTAG). Provides serial data for the boundary scan logic chain starting at SHARC_A.
TDI has a 20 kΩ internal pull-up resistor.
Test Data Output (JTAG). Serial scan output of the boundary scan chain path, from SHARC_D.
Test Reset (JTAG). (Common to all SHARCs) Resets the test state machine. TRST must be asserted
(pulsed low) after power-up or held low for proper operation of the AD14060/AD14060L. TRST has a
20 kΩ internal pull-up resistor.
Emulation Status. (Common to all SHARCs) Must be connected to the ADSP-2106x EZ-ICE target
board connector only.
Power Supply. Nominally +5.0 V dc for 5 V devices or +3.3 V dc for 3.3 V devices (26 pins).
Power Supply Return. (28 pins).
NOTES
FLAG3 is connected internally, common to SHARC_A, B, C, and D.
ID pins are hardwired internally as depicted in the block diagram.
1LINK PORTS 0, 2 and 5 are connected internally as described earlier in Link Port I/O.
2Three-statable only in EPROM boot mode (when BMS is an output).
REV. A
–11–
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