5962-9750701HXC View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'5962-9750701HXC' PDF : 44 Pages View PDF
AD14060/AD14060L
Memory Read—Bus Master
Use these specifications for asynchronous interfacing to memo-
ries (and memory-mapped peripherals) without reference to
CLKIN. These specifications apply when the AD14060/
AD14060L is the bus master accessing external memory space.
These switching characteristics also apply for bus master syn-
chronous read/write timing (see Synchronous Read/Write – Bus
Master below). If these timing requirements are met, the syn-
chronous read/write timing can be ignored (and vice versa).
Parameter
Timing Requirements:
tDAD
tDRLD
tHDA
tHDRH
tDAAK
tDSAK
Address, Delay to Data Valid1, 4
RD Low to Data Valid1
Data Hold from Address2
Data Hold from RD High2
ACK Delay from Address3, 4
ACK Delay from RD Low3
5V
Min
Max
3.3 V
Min
Max
Units
17.5 + DT + W
17.5 + DT + W ns
11.5 + 5DT/8 + W
11.5 + 5DT/8 + W ns
1
1
ns
2.5
2.5
ns
13.5 + 7DT/8 + W
13.5 + 7DT/8 + W ns
7.5 + DT/2 + W
7.5 + DT/2 + W ns
Switching Characteristics:
tDRHA
tDARL
tRW
tRWR
tSADADC
Address Hold After RD High
Address to RD Low4
RD Pulsewidth
RD High to WR, RD, DMAGx Low
Address Setup Before ADRCLK High4
–0.5 + H
1.5 + 3DT/8
12.5 + 5DT/8 + W
8 + 3DT/8 + HI
–0.5 + DT/4
–0.5 + H
ns
1.5 + 3DT/8
ns
12.5 + 5DT/8 + W
ns
8 + 3DT/8 + HI
ns
–0.5 + DT/4
ns
W = (number of wait states specified in WAIT register) Ă— tCK.
HI = tCK (if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise HI = 0).
H = tCK (if an address hold cycle occurs as specified in WAIT register; otherwise H = 0).
NOTES
1Data Delay/Setup: User must meet tDAD or tDRLD or synchronous spec tSSDATI.
2Data Hold: User must meet tHDA or tHDRH or synchronous spec tHDATI. See System Hold Time Calculation under Test Conditions for the calculation of hold times
given capacitive and dc loads.
3ACK Delay/Setup: User must meet tDSAK or tDAAK or synchronous specification tSACKC.
4For MSx, SW, BMS, the falling edge is referenced.
ADDRESS
MSx, SW
BMS
RD
DATA
ACK
tDARL
tRW
tDAAK
tDAD
tDRLD
tDSAK
tDRHA
tHDA
tHDRH
tRWR
WR, DMAG
ADRCLK
(OUT)
tSADADC
Figure 14. Memory Read—Bus Master
–18–
REV. A
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