5962-9750701HXC View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'5962-9750701HXC' PDF : 44 Pages View PDF
AD14060/AD14060L
Synchronous Read/Write—Bus Master
Use these specifications for interfacing to external memory
systems that require CLKIN—relative timing or for accessing a
slave ADSP-2106x (in multiprocessor memory space). These
synchronous switching characteristics are also valid during asyn-
chronous memory reads and writes (see Memory Read—Bus
Master and Memory Write—Bus Master).
When accessing a slave ADSP-2106x, these switching character-
istics must meet the slave’s timing requirements for synchronous
read/writes (see Synchronous Read/Write—Bus Slave). The
slave ADSP-2106x must also meet these (bus master) timing
requirements for data and acknowledge setup and hold times.
Parameter
Timing Requirements:
tSSDATI
tHSDATI
tDAAK
tSACKC
tHACKC
Data Setup Before CLKIN
Data Hold After CLKIN
ACK Delay After Address, MSx, SW, BMS1, 2
ACK Setup Before CLKIN2
ACK Hold After CLKIN
5V
Min
Max
3 + DT/8
4 – DT/8
6.5 + DT/4
–0.5 – DT/4
13.5 + 7 DT/8 + W
3.3 V
Min
Max
Units
3 + DT/8
ns
4 – DT/8
ns
13.5 + 7 DT/8 + W ns
6.5 + DT/4
ns
–0.5 – DT/4
ns
Switching Characteristics:
tDADRO
tHADRO
Address, MSx, BMS, SW Delay After CLKIN1
Address, MSx, BMS, SW Hold After CLKIN
tDPGC
tDRDO
tDWRO
tDRWL
PAGE Delay After CLKIN
RD High Delay After CLKIN
WR High Delay After CLKIN
RD/WR Low Delay After CLKIN
tSDDATO Data Delay After CLKIN
tDATTR Data Disable After CLKIN3
tDADCCK ADRCLK Delay After CLKIN
tADRCK ADRCLK Period
tADRCKH ADRCLK Width High
tADRCKL ADRCLK Width Low
8 – DT/8
–1 – DT/8
9 + DT/8 17 + DT/8
–2 – DT/8 5 – DT/8
–3 – 3DT/16 5 – 3DT/16
8 + DT/4 13.5 + DT/4
20 + 5DT/16
0 – DT/8 8 – DT/8
4 + DT/8 11 + DT/8
tCK
(tCK/2 – 2)
(tCK/2 – 2)
8 – DT/8
ns
–1 – DT/8
ns
9 + DT/8 17 + DT/8
ns
–2 – DT/8 5 – DT/8
ns
–3 – 3DT/16 5 – 3DT/16
ns
8 + DT/4 13.5 + DT/4
ns
20 + 5DT/16
ns
0 – DT/8 8 – DT/8
ns
4 + DT/8 11 + DT/8
ns
tCK
ns
(tCK/2 – 2)
ns
(tCK/2 – 2)
ns
W = (number of Wait states specified in WAIT register) × tCK.
NOTES
1For MSx, SW, BMS, the falling edge is referenced.
2ACK Delay/Setup: User must meet tDAAK or tDSAK or synchronous specification tSACKC.
3See System Hold Time Calculation under Test Conditions for calculation of hold times given capacitive and dc loads.
–20–
REV. A
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