ACPL-336J-000E View Datasheet(PDF) - Avago Technologies
Part Name
Description
MFG CO.
ACPL-336J-000E
Avago Technologies
'ACPL-336J-000E' PDF : 18 Pages View PDF
Table 6. Switching Specifications (AC)
Unless otherwise noted, all typical values at TA = 25 °C, VCC1 = 5 V, VCC2 – VEE2 = 30 V, VE – VEE2 = 0 V; all Minimum/
Maximum specifications are at Recommended Operating Conditions.
Parameter
Symbol
Min. Typ.* Max. Units Test Conditions
Fig. Note
Input LED to High Level Output
tPLH
Propagation Delay Time
50
130 220 ns RG = 10 Ω, CG = 10 nF,
11, 12, 1
f = 10 kHz, Duty Cycle = 50% 13
Input LED to Low Level Output
tPHL
Propagation Delay Time
50 155 250 ns
11, 12, 2
13
Pulse Width Distortion
PWD
25 120 ns
3, 4
Propagation Delay Difference
Between Any 2 Parts (tPHL-tPLH)
Propagation Delay Skew
10% to 90% Rise Time
90% to 10% Fall Time
DESAT Blanking Time
DESAT Sense to 90% VOUT Delay
DESAT Sense to 10% VOUT Delay
DESAT Sense to DESAT Low
Propagation Delay
PDD
-150
150 ns
tPSK
tR
tF
tDESAT(BLANKING)
tDESAT(90%)
tDESAT(10%)
tDESAT(LOW)
100 ns
80
ns
45
ns
0.6 1.1 µs
1.3 2
µs
4.8 6.5 µs
0.25
µs
RG = 10 Ω, CG= 10 nF
4, 5
4,6
24 7
24 8
24 9
24 10
DESAT Sense to Low Level FAULT
Signal Delay
tDESAT(FAULT)
2.2 5
µs RF = 10 kΩ, CF = Open
24 11
Output Mute Time due to DESAT
Time Input Kept Low Before Fault
Reset to High
tDESAT(MUTE)
2.3
tDESAT(RESET) 2.3
3.0 4.2 ms
3.0 4.2 ms RF = 10 kΩ, CF = Open
24 12
24 13
VCC2 to UVLO High Delay
tPLH_UVLO
10
µs
22 14
VCC2 to UVLO Low Delay
tPHL_UVLO
10
µs
22 15
VCC2 UVLO to VOUT High Delay
tUVLO_ON
5.3
µs
22 16
VCC2 UVLO to VOUT Low Delay
tUVLO_OFF
1
µs
22 17
Output High Level Common Mode |CMH|
Transient Immunity
30 >50
kV/µs TA = 25 °C, IF = 10 mA,
VCM = 1500 V, VCC2 = 30 V
14, 18, 20
16,18
Output Low Level Common Mode
Transient Immunity
|CML|
30 >50
kV/µs TA = 25 °C, IF = 0 mA,
15, 17, 19, 20
VCM = 1500 V, VCC2 = 30 V, 19
Notes:
1. tPLH is defined as propagation delay from 50% of LED input IF to 50% of High level output.
2. tPHL is defined as propagation delay from 50% of LED input IF to 50% of Low level output.
3. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH| for any given unit.
4. As measured from IF to VOUT.
5. The difference between tPHL and tPLH between any two ACPL-336J parts under the same test conditions.
6. tPSK is equal to the worst-case difference in tPHL and tPLH that will be seen between units under the same test condition.
7. The ACPL-336J internal delay time to respond to a DESAT fault condition without any external DESAT capacitor.
8. The amount of time from when DESAT threshold is exceeded to 90% of VGATE at mentioned test conditions.
9. The amount of time from when DESAT threshold is exceeded to 10% of VGATE at mentioned test conditions.
10. The amount of time from when DESAT threshold is exceeded to DESAT Low voltage, 0.7 V.
11. The amount of time from when DESAT threshold is exceeded to FAULT output Low – 50% of VCC1 voltage.
12. The amount of time when DESAT threshold is exceeded, output is muted to LED input.
13. The amount of time when DESAT mute time is expired, LED input must be kept low for FAULT status to return to High.
14. The delay time when VCC2 exceeds UVLO+ threshold to UVLO high – 50% of UVLO positive-going edge.
15. The delay time when VCC2 exceeds UVLO- threshold to UVLO low – 50% of UVLO negative-going edge.
16. The delay time when VCC2 exceeds UVLO+ threshold to 50% of high level output.
17. The delay time when VCC2 exceeds UVLO- threshold to 50% of low level output.
18. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output
will remain in the high state (i.e., VOUT > 15 V or FAULT > 2 V or UVLO > 2 V). A 330 pF and a 10 kΩ pull-up resistor are needed in FAULT and UVLO
detection mode.
19. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output
will remain in a low state (i.e., VOUT < 1.0 V or FAULT < 0.8 V or UVLO < 0.8 V).
20. Split resistor network in the ratio 1:1 at the anode and cathode. For further details, see description of input LED driver and split resistors circuit
section in the application notes.
7
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