ACS8514 View Datasheet(PDF) - Semtech Corporation

Part Name

Description

MFG CO.

ACS8514

Synchronous Equipment Timing Source Partner IC for 2nd T4 DPLL, Accurate Monitoring & Input Extender

Semtech Corporation 

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ACS8514 SETS Buddy

ADVANCED COMMS & SENSING FINAL

DATASHEET

Serial Mode

In SERIAL Mode, the device is configured to interface with a serial microprocessor bus. Figure 11 and Figure 12 show

the timing diagrams of write and read accesses for this mode. The serial interface can be SPI compatible.

The Motorola SPI convention is such that address and data is transmitted and received MSB first. On the ACS8514,

device address and data are transmitted and received LSB first. Address, read/write control and data on the SDI pin is

latched into the device on the rising edge of the SCLK. During a read operation, serial data output on the SDO pin can be

read out of the device on either the rising or falling edge of the SCLK depending on the logic level of CLKE. For standard

Motorola SPI compliance, data should be clocked out of the SDO pin on the rising edge of the SCLK so that it may be

latched into the microprocessor on the falling edge of the SCLK.

The serial interface clock (SCLK) is not required to run between accesses (i.e., when CSB = 1).

Figure 11 Read Access Timing in SERIAL Mode

Table 16 Read Access Timing in SERIAL Mode (For use with Figure 11 )

Symbol

tsu1

tsu2

td1

td2

Parameter

Setup SDI valid to SCLKrising edge

Setup CSBfalling edge to SCLKrising edge

Delay SCLKrising edge (SCLKfalling edge for CLKE = 1) to SDO valid

Delay CSBrising edge to SDO high-Z

MIN

4 ns

14 ns

-

-

Revision 3.00 April 2007 © Semtech Corp.

Page 26

TYP

MAX

-

-

-

-

-

18 ns

-

16 ns

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