ACS8514 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
ACS8514
Synchronous Equipment Timing Source Partner IC for 2nd T4 DPLL, Accurate Monitoring & Input Extender
Semtech Corporation
'ACS8514' PDF : 86 Pages View PDF
ACS8514 SETS Buddy
ADVANCED COMMS & SENSING FINAL
DATASHEET
Address(hex): 03 (continued)
Bit No.
6
5, 4
2
3,1,0
Description
disable_180
Normally the DPLLs will try to lock to the nearest
edge (±180°) for the first 2 seconds when locking to
a new reference. If the DPLL does not determine
that it is phase locked after this time, then the
capture range reverts to ±360°, which corresponds
to frequency and phase locking. Forcing the DPLL
into frequency locking mode may reduce the time to
frequency lock to a new reference by up to 2
seconds. However, this may cause an unnecessary
phase shift of up to 360° when the new and old
references are very close in frequency and phase.
Not used.
8k Edge Polarity
When lock 8k mode is selected for the current input
reference source, this bit allows the system to lock
on either the rising or the falling edge of the input
clock.
Test Control
Leave unchanged or set to zero
Bit Value
0
1
-
0
1
0
Value Description
Monitor DPLL automatically determines
frequency lock enable.
Monitor DPLL forced to always frequency and
phase lock.
-
Lock to falling clock edge.
Lock to rising clock edge.
-
Address(hex): 05
Register Name sts_interrupts
Description
(R/W) Bits [7:0] of the interrupt Default Value 1111 1111
status register.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I8
I7
I6
I5
I4
I3
I2
I1
Bit No.
Description
Bit Value Value Description
7
I8
0
Input I8 has not changed status (valid/invalid).
Interrupt indicating that input I8 has become valid (if
1
Input I8 has changed status (valid/invalid).
it was invalid), or invalid (if it was valid). Latched
Writing 1 resets the input to 0.
until reset by software writing a 1 to this bit.
6
I7
0
Input I7 has not changed status (valid/invalid).
Interrupt indicating that input I7 has become valid (if
1
Input I7 has changed status (valid/invalid).
it was invalid), or invalid (if it was valid). Latched
Writing 1 resets the input to 0.
until reset by software writing a 1 to this bit.
5
I6
0
Input I6 has not changed status (valid/invalid).
Interrupt indicating that input I6 has become valid (if
1
Input I6 has changed status (valid/invalid).
it was invalid), or invalid (if it was valid). Latched
Writing 1 resets the input to 0.
until reset by software writing a 1 to this bit.
4
I5
0
Input I5 has not changed status (valid/invalid).
Interrupt indicating that input I5 has become valid (if
1
Input I5 has changed status (valid/invalid).
it was invalid), or invalid (if it was valid). Latched
Writing 1 resets the input to 0.
until reset by software writing a 1 to this bit.
3
I4
0
Input I4 has not changed status (valid/invalid).
Interrupt indicating that input I4 has become valid (if
1
Input I4 has changed status (valid/invalid).
it was invalid), or invalid (if it was valid). Latched
Writing 1 resets the input to 0.
until reset by software writing a 1 to this bit.
Revision 3.00 April 2007 © Semtech Corp.
Page 33
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